// SPDX-FileCopyrightText: © 2025 Tenstorrent AI ULC
//
// SPDX-License-Identifier: Apache-2.0

#ifndef OVERLAY_REG_DEFINES_CORE_H
#define OVERLAY_REG_DEFINES_CORE_H

#include <stdint.h>

//==============================================================================
// Addresses for Address Map: overlay
//==============================================================================

#define OVERLAY_REG_MAP_BASE_ADDR (0x00000000)
#define OVERLAY_REG_MAP_SIZE (0x08207008)

//==============================================================================
// Addresses for Address Map: memory_port_cacheable
//==============================================================================

#define MEMORY_PORT_CACHEABLE_REG_MAP_BASE_ADDR (0x00000000)
#define MEMORY_PORT_CACHEABLE_REG_MAP_SIZE (0x00400000)

//==============================================================================
// Memory: mem_port
//==============================================================================

#define MEMORY_PORT_CACHEABLE_MEM_PORT_MEM_BASE_ADDR (0x00000000)
#define MEMORY_PORT_CACHEABLE_MEM_PORT_MEM_SIZE (0x00400000)

//==============================================================================
// Addresses for Address Map: memory_port_noncacheable
//==============================================================================

#define MEMORY_PORT_NONCACHEABLE_REG_MAP_BASE_ADDR (0x00400000)
#define MEMORY_PORT_NONCACHEABLE_REG_MAP_SIZE (0x00400000)

//==============================================================================
// Memory: mem_port
//==============================================================================

#define MEMORY_PORT_NONCACHEABLE_MEM_PORT_MEM_BASE_ADDR (0x00400000)
#define MEMORY_PORT_NONCACHEABLE_MEM_PORT_MEM_SIZE (0x00400000)

//==============================================================================
// Addresses for Address Map: edc_biu_map
//==============================================================================

#define EDC_BIU_MAP_REG_MAP_BASE_ADDR (0x01800000)
#define EDC_BIU_MAP_REG_MAP_SIZE (0x00000040)

//==============================================================================
// Register File: edc_biu
//==============================================================================

#define EDC_BIU_MAP_EDC_BIU_REG_FILE_BASE_ADDR (0x01800000)
#define EDC_BIU_MAP_EDC_BIU_REG_FILE_SIZE (0x00000040)

#define EDC_BIU_MAP_EDC_BIU_ID_REG_OFFSET (0x00000000)
#define EDC_BIU_MAP_EDC_BIU_ID_REG_ADDR (0x01800000)
#define EDC_BIU_MAP_EDC_BIU_STAT_REG_OFFSET (0x00000004)
#define EDC_BIU_MAP_EDC_BIU_STAT_REG_ADDR (0x01800004)
#define EDC_BIU_MAP_EDC_BIU_CTRL_REG_OFFSET (0x00000008)
#define EDC_BIU_MAP_EDC_BIU_CTRL_REG_ADDR (0x01800008)
#define EDC_BIU_MAP_EDC_BIU_IRQ_EN_REG_OFFSET (0x0000000C)
#define EDC_BIU_MAP_EDC_BIU_IRQ_EN_REG_ADDR (0x0180000C)
#define EDC_BIU_MAP_EDC_BIU_RSP_HDR0_REG_OFFSET (0x00000010)
#define EDC_BIU_MAP_EDC_BIU_RSP_HDR0_REG_ADDR (0x01800010)
#define EDC_BIU_MAP_EDC_BIU_RSP_HDR1_REG_OFFSET (0x00000014)
#define EDC_BIU_MAP_EDC_BIU_RSP_HDR1_REG_ADDR (0x01800014)
#define EDC_BIU_MAP_EDC_BIU_RSP_DATA_0__REG_OFFSET (0x00000018)
#define EDC_BIU_MAP_EDC_BIU_RSP_DATA_0__REG_ADDR (0x01800018)
#define EDC_BIU_MAP_EDC_BIU_RSP_DATA_1__REG_OFFSET (0x0000001C)
#define EDC_BIU_MAP_EDC_BIU_RSP_DATA_1__REG_ADDR (0x0180001C)
#define EDC_BIU_MAP_EDC_BIU_RSP_DATA_2__REG_OFFSET (0x00000020)
#define EDC_BIU_MAP_EDC_BIU_RSP_DATA_2__REG_ADDR (0x01800020)
#define EDC_BIU_MAP_EDC_BIU_RSP_DATA_3__REG_OFFSET (0x00000024)
#define EDC_BIU_MAP_EDC_BIU_RSP_DATA_3__REG_ADDR (0x01800024)
#define EDC_BIU_MAP_EDC_BIU_REQ_HDR0_REG_OFFSET (0x00000028)
#define EDC_BIU_MAP_EDC_BIU_REQ_HDR0_REG_ADDR (0x01800028)
#define EDC_BIU_MAP_EDC_BIU_REQ_HDR1_REG_OFFSET (0x0000002C)
#define EDC_BIU_MAP_EDC_BIU_REQ_HDR1_REG_ADDR (0x0180002C)
#define EDC_BIU_MAP_EDC_BIU_REQ_DATA_0__REG_OFFSET (0x00000030)
#define EDC_BIU_MAP_EDC_BIU_REQ_DATA_0__REG_ADDR (0x01800030)
#define EDC_BIU_MAP_EDC_BIU_REQ_DATA_1__REG_OFFSET (0x00000034)
#define EDC_BIU_MAP_EDC_BIU_REQ_DATA_1__REG_ADDR (0x01800034)
#define EDC_BIU_MAP_EDC_BIU_REQ_DATA_2__REG_OFFSET (0x00000038)
#define EDC_BIU_MAP_EDC_BIU_REQ_DATA_2__REG_ADDR (0x01800038)
#define EDC_BIU_MAP_EDC_BIU_REQ_DATA_3__REG_OFFSET (0x0000003C)
#define EDC_BIU_MAP_EDC_BIU_REQ_DATA_3__REG_ADDR (0x0180003C)

//==============================================================================
// Addresses for Address Map: tt_cluster_ctrl
//==============================================================================

#define TT_CLUSTER_CTRL_REG_MAP_BASE_ADDR (0x03000000)
#define TT_CLUSTER_CTRL_REG_MAP_SIZE (0x00000384)

#define TT_CLUSTER_CTRL_RESET_VECTOR_0__REG_OFFSET (0x00000000)
#define TT_CLUSTER_CTRL_RESET_VECTOR_0__REG_ADDR (0x03000000)
#define TT_CLUSTER_CTRL_RESET_VECTOR_1__REG_OFFSET (0x00000008)
#define TT_CLUSTER_CTRL_RESET_VECTOR_1__REG_ADDR (0x03000008)
#define TT_CLUSTER_CTRL_RESET_VECTOR_2__REG_OFFSET (0x00000010)
#define TT_CLUSTER_CTRL_RESET_VECTOR_2__REG_ADDR (0x03000010)
#define TT_CLUSTER_CTRL_RESET_VECTOR_3__REG_OFFSET (0x00000018)
#define TT_CLUSTER_CTRL_RESET_VECTOR_3__REG_ADDR (0x03000018)
#define TT_CLUSTER_CTRL_RESET_VECTOR_4__REG_OFFSET (0x00000020)
#define TT_CLUSTER_CTRL_RESET_VECTOR_4__REG_ADDR (0x03000020)
#define TT_CLUSTER_CTRL_RESET_VECTOR_5__REG_OFFSET (0x00000028)
#define TT_CLUSTER_CTRL_RESET_VECTOR_5__REG_ADDR (0x03000028)
#define TT_CLUSTER_CTRL_RESET_VECTOR_6__REG_OFFSET (0x00000030)
#define TT_CLUSTER_CTRL_RESET_VECTOR_6__REG_ADDR (0x03000030)
#define TT_CLUSTER_CTRL_RESET_VECTOR_7__REG_OFFSET (0x00000038)
#define TT_CLUSTER_CTRL_RESET_VECTOR_7__REG_ADDR (0x03000038)
#define TT_CLUSTER_CTRL_SCRATCH_0__REG_OFFSET (0x00000040)
#define TT_CLUSTER_CTRL_SCRATCH_0__REG_ADDR (0x03000040)
#define TT_CLUSTER_CTRL_SCRATCH_1__REG_OFFSET (0x00000044)
#define TT_CLUSTER_CTRL_SCRATCH_1__REG_ADDR (0x03000044)
#define TT_CLUSTER_CTRL_SCRATCH_2__REG_OFFSET (0x00000048)
#define TT_CLUSTER_CTRL_SCRATCH_2__REG_ADDR (0x03000048)
#define TT_CLUSTER_CTRL_SCRATCH_3__REG_OFFSET (0x0000004C)
#define TT_CLUSTER_CTRL_SCRATCH_3__REG_ADDR (0x0300004C)
#define TT_CLUSTER_CTRL_SCRATCH_4__REG_OFFSET (0x00000050)
#define TT_CLUSTER_CTRL_SCRATCH_4__REG_ADDR (0x03000050)
#define TT_CLUSTER_CTRL_SCRATCH_5__REG_OFFSET (0x00000054)
#define TT_CLUSTER_CTRL_SCRATCH_5__REG_ADDR (0x03000054)
#define TT_CLUSTER_CTRL_SCRATCH_6__REG_OFFSET (0x00000058)
#define TT_CLUSTER_CTRL_SCRATCH_6__REG_ADDR (0x03000058)
#define TT_CLUSTER_CTRL_SCRATCH_7__REG_OFFSET (0x0000005C)
#define TT_CLUSTER_CTRL_SCRATCH_7__REG_ADDR (0x0300005C)
#define TT_CLUSTER_CTRL_SCRATCH_8__REG_OFFSET (0x00000060)
#define TT_CLUSTER_CTRL_SCRATCH_8__REG_ADDR (0x03000060)
#define TT_CLUSTER_CTRL_SCRATCH_9__REG_OFFSET (0x00000064)
#define TT_CLUSTER_CTRL_SCRATCH_9__REG_ADDR (0x03000064)
#define TT_CLUSTER_CTRL_SCRATCH_10__REG_OFFSET (0x00000068)
#define TT_CLUSTER_CTRL_SCRATCH_10__REG_ADDR (0x03000068)
#define TT_CLUSTER_CTRL_SCRATCH_11__REG_OFFSET (0x0000006C)
#define TT_CLUSTER_CTRL_SCRATCH_11__REG_ADDR (0x0300006C)
#define TT_CLUSTER_CTRL_SCRATCH_12__REG_OFFSET (0x00000070)
#define TT_CLUSTER_CTRL_SCRATCH_12__REG_ADDR (0x03000070)
#define TT_CLUSTER_CTRL_SCRATCH_13__REG_OFFSET (0x00000074)
#define TT_CLUSTER_CTRL_SCRATCH_13__REG_ADDR (0x03000074)
#define TT_CLUSTER_CTRL_SCRATCH_14__REG_OFFSET (0x00000078)
#define TT_CLUSTER_CTRL_SCRATCH_14__REG_ADDR (0x03000078)
#define TT_CLUSTER_CTRL_SCRATCH_15__REG_OFFSET (0x0000007C)
#define TT_CLUSTER_CTRL_SCRATCH_15__REG_ADDR (0x0300007C)
#define TT_CLUSTER_CTRL_SCRATCH_16__REG_OFFSET (0x00000080)
#define TT_CLUSTER_CTRL_SCRATCH_16__REG_ADDR (0x03000080)
#define TT_CLUSTER_CTRL_SCRATCH_17__REG_OFFSET (0x00000084)
#define TT_CLUSTER_CTRL_SCRATCH_17__REG_ADDR (0x03000084)
#define TT_CLUSTER_CTRL_SCRATCH_18__REG_OFFSET (0x00000088)
#define TT_CLUSTER_CTRL_SCRATCH_18__REG_ADDR (0x03000088)
#define TT_CLUSTER_CTRL_SCRATCH_19__REG_OFFSET (0x0000008C)
#define TT_CLUSTER_CTRL_SCRATCH_19__REG_ADDR (0x0300008C)
#define TT_CLUSTER_CTRL_SCRATCH_20__REG_OFFSET (0x00000090)
#define TT_CLUSTER_CTRL_SCRATCH_20__REG_ADDR (0x03000090)
#define TT_CLUSTER_CTRL_SCRATCH_21__REG_OFFSET (0x00000094)
#define TT_CLUSTER_CTRL_SCRATCH_21__REG_ADDR (0x03000094)
#define TT_CLUSTER_CTRL_SCRATCH_22__REG_OFFSET (0x00000098)
#define TT_CLUSTER_CTRL_SCRATCH_22__REG_ADDR (0x03000098)
#define TT_CLUSTER_CTRL_SCRATCH_23__REG_OFFSET (0x0000009C)
#define TT_CLUSTER_CTRL_SCRATCH_23__REG_ADDR (0x0300009C)
#define TT_CLUSTER_CTRL_SCRATCH_24__REG_OFFSET (0x000000A0)
#define TT_CLUSTER_CTRL_SCRATCH_24__REG_ADDR (0x030000A0)
#define TT_CLUSTER_CTRL_SCRATCH_25__REG_OFFSET (0x000000A4)
#define TT_CLUSTER_CTRL_SCRATCH_25__REG_ADDR (0x030000A4)
#define TT_CLUSTER_CTRL_SCRATCH_26__REG_OFFSET (0x000000A8)
#define TT_CLUSTER_CTRL_SCRATCH_26__REG_ADDR (0x030000A8)
#define TT_CLUSTER_CTRL_SCRATCH_27__REG_OFFSET (0x000000AC)
#define TT_CLUSTER_CTRL_SCRATCH_27__REG_ADDR (0x030000AC)
#define TT_CLUSTER_CTRL_SCRATCH_28__REG_OFFSET (0x000000B0)
#define TT_CLUSTER_CTRL_SCRATCH_28__REG_ADDR (0x030000B0)
#define TT_CLUSTER_CTRL_SCRATCH_29__REG_OFFSET (0x000000B4)
#define TT_CLUSTER_CTRL_SCRATCH_29__REG_ADDR (0x030000B4)
#define TT_CLUSTER_CTRL_SCRATCH_30__REG_OFFSET (0x000000B8)
#define TT_CLUSTER_CTRL_SCRATCH_30__REG_ADDR (0x030000B8)
#define TT_CLUSTER_CTRL_SCRATCH_31__REG_OFFSET (0x000000BC)
#define TT_CLUSTER_CTRL_SCRATCH_31__REG_ADDR (0x030000BC)
#define TT_CLUSTER_CTRL_ROCC_MEM_CHICKEN_REG_OFFSET (0x000000C0)
#define TT_CLUSTER_CTRL_ROCC_MEM_CHICKEN_REG_ADDR (0x030000C0)
#define TT_CLUSTER_CTRL_SCATTER_LIST_MAGIC_NUM_LO_REG_OFFSET (0x000000C4)
#define TT_CLUSTER_CTRL_SCATTER_LIST_MAGIC_NUM_LO_REG_ADDR (0x030000C4)
#define TT_CLUSTER_CTRL_SCATTER_LIST_MAGIC_NUM_HI_REG_OFFSET (0x000000C8)
#define TT_CLUSTER_CTRL_SCATTER_LIST_MAGIC_NUM_HI_REG_ADDR (0x030000C8)
#define TT_CLUSTER_CTRL_CLOCK_GATING_REG_OFFSET (0x000000CC)
#define TT_CLUSTER_CTRL_CLOCK_GATING_REG_ADDR (0x030000CC)
#define TT_CLUSTER_CTRL_CLOCK_GATING_HYST_REG_OFFSET (0x000000D0)
#define TT_CLUSTER_CTRL_CLOCK_GATING_HYST_REG_ADDR (0x030000D0)
#define TT_CLUSTER_CTRL_WB_PC_REG_C0_REG_OFFSET (0x000000D8)
#define TT_CLUSTER_CTRL_WB_PC_REG_C0_REG_ADDR (0x030000D8)
#define TT_CLUSTER_CTRL_WB_PC_REG_C1_REG_OFFSET (0x000000E0)
#define TT_CLUSTER_CTRL_WB_PC_REG_C1_REG_ADDR (0x030000E0)
#define TT_CLUSTER_CTRL_WB_PC_REG_C2_REG_OFFSET (0x000000E8)
#define TT_CLUSTER_CTRL_WB_PC_REG_C2_REG_ADDR (0x030000E8)
#define TT_CLUSTER_CTRL_WB_PC_REG_C3_REG_OFFSET (0x000000F0)
#define TT_CLUSTER_CTRL_WB_PC_REG_C3_REG_ADDR (0x030000F0)
#define TT_CLUSTER_CTRL_WB_PC_REG_C4_REG_OFFSET (0x000000F8)
#define TT_CLUSTER_CTRL_WB_PC_REG_C4_REG_ADDR (0x030000F8)
#define TT_CLUSTER_CTRL_WB_PC_REG_C5_REG_OFFSET (0x00000100)
#define TT_CLUSTER_CTRL_WB_PC_REG_C5_REG_ADDR (0x03000100)
#define TT_CLUSTER_CTRL_WB_PC_REG_C6_REG_OFFSET (0x00000108)
#define TT_CLUSTER_CTRL_WB_PC_REG_C6_REG_ADDR (0x03000108)
#define TT_CLUSTER_CTRL_WB_PC_REG_C7_REG_OFFSET (0x00000110)
#define TT_CLUSTER_CTRL_WB_PC_REG_C7_REG_ADDR (0x03000110)
#define TT_CLUSTER_CTRL_WB_PC_CTRL_REG_OFFSET (0x00000118)
#define TT_CLUSTER_CTRL_WB_PC_CTRL_REG_ADDR (0x03000118)
#define TT_CLUSTER_CTRL_ECC_PARITY_CONTROL_REG_OFFSET (0x0000011C)
#define TT_CLUSTER_CTRL_ECC_PARITY_CONTROL_REG_ADDR (0x0300011C)
#define TT_CLUSTER_CTRL_ECC_PARITY_STATUS_REG_OFFSET (0x00000120)
#define TT_CLUSTER_CTRL_ECC_PARITY_STATUS_REG_ADDR (0x03000120)
#define TT_CLUSTER_CTRL_NOC_SNOOP_TL_MASTER_CFG_REG_OFFSET (0x00000124)
#define TT_CLUSTER_CTRL_NOC_SNOOP_TL_MASTER_CFG_REG_ADDR (0x03000124)
#define TT_CLUSTER_CTRL_ASSERTS_REG_OFFSET (0x00000128)
#define TT_CLUSTER_CTRL_ASSERTS_REG_ADDR (0x03000128)
#define TT_CLUSTER_CTRL_PREFETCHER_CONTROL_REG_OFFSET (0x0000012C)
#define TT_CLUSTER_CTRL_PREFETCHER_CONTROL_REG_ADDR (0x0300012C)
#define TT_CLUSTER_CTRL_BUS_ERROR_UNIT_DATA_C0_REG_OFFSET (0x00000130)
#define TT_CLUSTER_CTRL_BUS_ERROR_UNIT_DATA_C0_REG_ADDR (0x03000130)
#define TT_CLUSTER_CTRL_BUS_ERROR_UNIT_DATA_C1_REG_OFFSET (0x00000138)
#define TT_CLUSTER_CTRL_BUS_ERROR_UNIT_DATA_C1_REG_ADDR (0x03000138)
#define TT_CLUSTER_CTRL_BUS_ERROR_UNIT_DATA_C2_REG_OFFSET (0x00000140)
#define TT_CLUSTER_CTRL_BUS_ERROR_UNIT_DATA_C2_REG_ADDR (0x03000140)
#define TT_CLUSTER_CTRL_BUS_ERROR_UNIT_DATA_C3_REG_OFFSET (0x00000148)
#define TT_CLUSTER_CTRL_BUS_ERROR_UNIT_DATA_C3_REG_ADDR (0x03000148)
#define TT_CLUSTER_CTRL_BUS_ERROR_UNIT_DATA_C4_REG_OFFSET (0x00000150)
#define TT_CLUSTER_CTRL_BUS_ERROR_UNIT_DATA_C4_REG_ADDR (0x03000150)
#define TT_CLUSTER_CTRL_BUS_ERROR_UNIT_DATA_C5_REG_OFFSET (0x00000158)
#define TT_CLUSTER_CTRL_BUS_ERROR_UNIT_DATA_C5_REG_ADDR (0x03000158)
#define TT_CLUSTER_CTRL_BUS_ERROR_UNIT_DATA_C6_REG_OFFSET (0x00000160)
#define TT_CLUSTER_CTRL_BUS_ERROR_UNIT_DATA_C6_REG_ADDR (0x03000160)
#define TT_CLUSTER_CTRL_BUS_ERROR_UNIT_DATA_C7_REG_OFFSET (0x00000168)
#define TT_CLUSTER_CTRL_BUS_ERROR_UNIT_DATA_C7_REG_ADDR (0x03000168)
#define TT_CLUSTER_CTRL_L2_DIR_ERRORS_0__REG_OFFSET (0x00000170)
#define TT_CLUSTER_CTRL_L2_DIR_ERRORS_0__REG_ADDR (0x03000170)
#define TT_CLUSTER_CTRL_L2_DIR_ERRORS_1__REG_OFFSET (0x00000174)
#define TT_CLUSTER_CTRL_L2_DIR_ERRORS_1__REG_ADDR (0x03000174)
#define TT_CLUSTER_CTRL_L2_DIR_ERRORS_2__REG_OFFSET (0x00000178)
#define TT_CLUSTER_CTRL_L2_DIR_ERRORS_2__REG_ADDR (0x03000178)
#define TT_CLUSTER_CTRL_L2_DIR_ERRORS_3__REG_OFFSET (0x0000017C)
#define TT_CLUSTER_CTRL_L2_DIR_ERRORS_3__REG_ADDR (0x0300017C)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_0__REG_OFFSET (0x00000180)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_0__REG_ADDR (0x03000180)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_1__REG_OFFSET (0x00000184)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_1__REG_ADDR (0x03000184)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_2__REG_OFFSET (0x00000188)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_2__REG_ADDR (0x03000188)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_3__REG_OFFSET (0x0000018C)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_3__REG_ADDR (0x0300018C)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_4__REG_OFFSET (0x00000190)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_4__REG_ADDR (0x03000190)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_5__REG_OFFSET (0x00000194)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_5__REG_ADDR (0x03000194)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_6__REG_OFFSET (0x00000198)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_6__REG_ADDR (0x03000198)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_7__REG_OFFSET (0x0000019C)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_7__REG_ADDR (0x0300019C)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_8__REG_OFFSET (0x000001A0)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_8__REG_ADDR (0x030001A0)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_9__REG_OFFSET (0x000001A4)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_9__REG_ADDR (0x030001A4)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_10__REG_OFFSET (0x000001A8)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_10__REG_ADDR (0x030001A8)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_11__REG_OFFSET (0x000001AC)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_11__REG_ADDR (0x030001AC)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_12__REG_OFFSET (0x000001B0)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_12__REG_ADDR (0x030001B0)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_13__REG_OFFSET (0x000001B4)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_13__REG_ADDR (0x030001B4)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_14__REG_OFFSET (0x000001B8)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_14__REG_ADDR (0x030001B8)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_15__REG_OFFSET (0x000001BC)
#define TT_CLUSTER_CTRL_L2_BANKS_ERRORS_15__REG_ADDR (0x030001BC)
#define TT_CLUSTER_CTRL_DEBUG_DMACTIVE_REG_OFFSET (0x000001C0)
#define TT_CLUSTER_CTRL_DEBUG_DMACTIVE_REG_ADDR (0x030001C0)
#define TT_CLUSTER_CTRL_DEBUG_DMACTIVEACK_REG_OFFSET (0x000001C4)
#define TT_CLUSTER_CTRL_DEBUG_DMACTIVEACK_REG_ADDR (0x030001C4)

//==============================================================================
// Register File: t6_l1_csr
//==============================================================================

#define TT_CLUSTER_CTRL_T6_L1_CSR_REG_FILE_BASE_ADDR (0x03000200)
#define TT_CLUSTER_CTRL_T6_L1_CSR_REG_FILE_SIZE (0x00000174)

#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN_CTRL_REG_OFFSET (0x00000000)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN_CTRL_REG_ADDR (0x03000200)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_MASK_REG_OFFSET (0x00000004)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_MASK_REG_ADDR (0x03000204)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_MATCH_REG_OFFSET (0x00000008)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_MATCH_REG_ADDR (0x03000208)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_ADDR4_REG_OFFSET (0x0000000C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_ADDR4_REG_ADDR (0x0300020C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_ADDR5_REG_OFFSET (0x00000010)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_ADDR5_REG_ADDR (0x03000210)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_ADDR6_REG_OFFSET (0x00000014)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_ADDR6_REG_ADDR (0x03000214)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_ADDR7_REG_OFFSET (0x00000018)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_ADDR7_REG_ADDR (0x03000218)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_ADDR8_REG_OFFSET (0x0000001C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_ADDR8_REG_ADDR (0x0300021C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_ADDR9_REG_OFFSET (0x00000020)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_ADDR9_REG_ADDR (0x03000220)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_ADDR10_REG_OFFSET (0x00000024)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_ADDR10_REG_ADDR (0x03000224)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_ADDR11_REG_OFFSET (0x00000028)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_ADDR11_REG_ADDR (0x03000228)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_SWAP_ADDR10_REG_OFFSET (0x0000002C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_SWAP_ADDR10_REG_ADDR (0x0300022C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_SWAP_ADDR11_REG_OFFSET (0x00000030)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_SWAP_ADDR11_REG_ADDR (0x03000230)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_SWAP_ADDR12_REG_OFFSET (0x00000034)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_SWAP_ADDR12_REG_ADDR (0x03000234)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_SWAP_ADDR13_REG_OFFSET (0x00000038)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_SWAP_ADDR13_REG_ADDR (0x03000238)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_SWAP_ADDR14_REG_OFFSET (0x0000003C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_SWAP_ADDR14_REG_ADDR (0x0300023C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_SWAP_ADDR15_REG_OFFSET (0x00000040)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_SWAP_ADDR15_REG_ADDR (0x03000240)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_SWAP_ADDR16_REG_OFFSET (0x00000044)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_SWAP_ADDR16_REG_ADDR (0x03000244)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_SWAP_ADDR17_REG_OFFSET (0x00000048)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_SWAP_ADDR17_REG_ADDR (0x03000248)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_SWAP_ADDR18_REG_OFFSET (0x0000004C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_SWAP_ADDR18_REG_ADDR (0x0300024C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_SWAP_ADDR19_REG_OFFSET (0x00000050)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_SWAP_ADDR19_REG_ADDR (0x03000250)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_SWAP_ADDR20_REG_OFFSET (0x00000054)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_SWAP_ADDR20_REG_ADDR (0x03000254)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_SWAP_ADDR21_REG_OFFSET (0x00000058)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN0_SWAP_ADDR21_REG_ADDR (0x03000258)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_MASK_REG_OFFSET (0x0000005C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_MASK_REG_ADDR (0x0300025C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_MATCH_REG_OFFSET (0x00000060)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_MATCH_REG_ADDR (0x03000260)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_ADDR4_REG_OFFSET (0x00000064)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_ADDR4_REG_ADDR (0x03000264)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_ADDR5_REG_OFFSET (0x00000068)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_ADDR5_REG_ADDR (0x03000268)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_ADDR6_REG_OFFSET (0x0000006C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_ADDR6_REG_ADDR (0x0300026C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_ADDR7_REG_OFFSET (0x00000070)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_ADDR7_REG_ADDR (0x03000270)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_ADDR8_REG_OFFSET (0x00000074)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_ADDR8_REG_ADDR (0x03000274)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_ADDR9_REG_OFFSET (0x00000078)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_ADDR9_REG_ADDR (0x03000278)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_ADDR10_REG_OFFSET (0x0000007C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_ADDR10_REG_ADDR (0x0300027C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_ADDR11_REG_OFFSET (0x00000080)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_ADDR11_REG_ADDR (0x03000280)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_SWAP_ADDR10_REG_OFFSET (0x00000084)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_SWAP_ADDR10_REG_ADDR (0x03000284)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_SWAP_ADDR11_REG_OFFSET (0x00000088)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_SWAP_ADDR11_REG_ADDR (0x03000288)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_SWAP_ADDR12_REG_OFFSET (0x0000008C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_SWAP_ADDR12_REG_ADDR (0x0300028C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_SWAP_ADDR13_REG_OFFSET (0x00000090)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_SWAP_ADDR13_REG_ADDR (0x03000290)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_SWAP_ADDR14_REG_OFFSET (0x00000094)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_SWAP_ADDR14_REG_ADDR (0x03000294)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_SWAP_ADDR15_REG_OFFSET (0x00000098)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_SWAP_ADDR15_REG_ADDR (0x03000298)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_SWAP_ADDR16_REG_OFFSET (0x0000009C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_SWAP_ADDR16_REG_ADDR (0x0300029C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_SWAP_ADDR17_REG_OFFSET (0x000000A0)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_SWAP_ADDR17_REG_ADDR (0x030002A0)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_SWAP_ADDR18_REG_OFFSET (0x000000A4)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_SWAP_ADDR18_REG_ADDR (0x030002A4)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_SWAP_ADDR19_REG_OFFSET (0x000000A8)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_SWAP_ADDR19_REG_ADDR (0x030002A8)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_SWAP_ADDR20_REG_OFFSET (0x000000AC)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_SWAP_ADDR20_REG_ADDR (0x030002AC)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_SWAP_ADDR21_REG_OFFSET (0x000000B0)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_HASH_FN1_SWAP_ADDR21_REG_ADDR (0x030002B0)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_PERF_CTRL_REG_OFFSET (0x000000B4)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_PERF_CTRL_REG_ADDR (0x030002B4)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_PERF_CNT_REG_OFFSET (0x000000B8)
#define TT_CLUSTER_CTRL_T6_L1_CSR_GROUP_PERF_CNT_REG_ADDR (0x030002B8)
#define TT_CLUSTER_CTRL_T6_L1_CSR_IN_ORDER_MASK_REG_OFFSET (0x000000BC)
#define TT_CLUSTER_CTRL_T6_L1_CSR_IN_ORDER_MASK_REG_ADDR (0x030002BC)
#define TT_CLUSTER_CTRL_T6_L1_CSR_IN_ORDER_MATCH_REG_OFFSET (0x000000C0)
#define TT_CLUSTER_CTRL_T6_L1_CSR_IN_ORDER_MATCH_REG_ADDR (0x030002C0)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RW_PORT_CTRL_0__REG_OFFSET (0x000000C4)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RW_PORT_CTRL_0__REG_ADDR (0x030002C4)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RW_PORT_CTRL_1__REG_OFFSET (0x000000C8)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RW_PORT_CTRL_1__REG_ADDR (0x030002C8)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RW_PORT_CTRL_2__REG_OFFSET (0x000000CC)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RW_PORT_CTRL_2__REG_ADDR (0x030002CC)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RW_PORT_CTRL_3__REG_OFFSET (0x000000D0)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RW_PORT_CTRL_3__REG_ADDR (0x030002D0)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RW_PORT_CTRL_4__REG_OFFSET (0x000000D4)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RW_PORT_CTRL_4__REG_ADDR (0x030002D4)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RW_PORT_CTRL_5__REG_OFFSET (0x000000D8)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RW_PORT_CTRL_5__REG_ADDR (0x030002D8)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RW_PORT_STATUS_0__REG_OFFSET (0x000000DC)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RW_PORT_STATUS_0__REG_ADDR (0x030002DC)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RW_PORT_STATUS_1__REG_OFFSET (0x000000E0)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RW_PORT_STATUS_1__REG_ADDR (0x030002E0)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RW_PORT_STATUS_2__REG_OFFSET (0x000000E4)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RW_PORT_STATUS_2__REG_ADDR (0x030002E4)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RW_PORT_STATUS_3__REG_OFFSET (0x000000E8)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RW_PORT_STATUS_3__REG_ADDR (0x030002E8)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RW_PORT_STATUS_4__REG_OFFSET (0x000000EC)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RW_PORT_STATUS_4__REG_ADDR (0x030002EC)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RW_PORT_STATUS_5__REG_OFFSET (0x000000F0)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RW_PORT_STATUS_5__REG_ADDR (0x030002F0)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_CTRL_0__REG_OFFSET (0x000000F4)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_CTRL_0__REG_ADDR (0x030002F4)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_CTRL_1__REG_OFFSET (0x000000F8)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_CTRL_1__REG_ADDR (0x030002F8)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_CTRL_2__REG_OFFSET (0x000000FC)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_CTRL_2__REG_ADDR (0x030002FC)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_CTRL_3__REG_OFFSET (0x00000100)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_CTRL_3__REG_ADDR (0x03000300)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_CTRL_4__REG_OFFSET (0x00000104)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_CTRL_4__REG_ADDR (0x03000304)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_CTRL_5__REG_OFFSET (0x00000108)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_CTRL_5__REG_ADDR (0x03000308)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_CTRL_6__REG_OFFSET (0x0000010C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_CTRL_6__REG_ADDR (0x0300030C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_CTRL_7__REG_OFFSET (0x00000110)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_CTRL_7__REG_ADDR (0x03000310)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_STATUS_0__REG_OFFSET (0x00000114)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_STATUS_0__REG_ADDR (0x03000314)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_STATUS_1__REG_OFFSET (0x00000118)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_STATUS_1__REG_ADDR (0x03000318)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_STATUS_2__REG_OFFSET (0x0000011C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_STATUS_2__REG_ADDR (0x0300031C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_STATUS_3__REG_OFFSET (0x00000120)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_STATUS_3__REG_ADDR (0x03000320)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_STATUS_4__REG_OFFSET (0x00000124)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_STATUS_4__REG_ADDR (0x03000324)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_STATUS_5__REG_OFFSET (0x00000128)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_STATUS_5__REG_ADDR (0x03000328)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_STATUS_6__REG_OFFSET (0x0000012C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_STATUS_6__REG_ADDR (0x0300032C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_STATUS_7__REG_OFFSET (0x00000130)
#define TT_CLUSTER_CTRL_T6_L1_CSR_RD_PORT_STATUS_7__REG_ADDR (0x03000330)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_CTRL_0__REG_OFFSET (0x00000134)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_CTRL_0__REG_ADDR (0x03000334)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_CTRL_1__REG_OFFSET (0x00000138)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_CTRL_1__REG_ADDR (0x03000338)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_CTRL_2__REG_OFFSET (0x0000013C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_CTRL_2__REG_ADDR (0x0300033C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_CTRL_3__REG_OFFSET (0x00000140)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_CTRL_3__REG_ADDR (0x03000340)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_CTRL_4__REG_OFFSET (0x00000144)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_CTRL_4__REG_ADDR (0x03000344)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_CTRL_5__REG_OFFSET (0x00000148)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_CTRL_5__REG_ADDR (0x03000348)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_CTRL_6__REG_OFFSET (0x0000014C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_CTRL_6__REG_ADDR (0x0300034C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_CTRL_7__REG_OFFSET (0x00000150)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_CTRL_7__REG_ADDR (0x03000350)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_STATUS_0__REG_OFFSET (0x00000154)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_STATUS_0__REG_ADDR (0x03000354)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_STATUS_1__REG_OFFSET (0x00000158)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_STATUS_1__REG_ADDR (0x03000358)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_STATUS_2__REG_OFFSET (0x0000015C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_STATUS_2__REG_ADDR (0x0300035C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_STATUS_3__REG_OFFSET (0x00000160)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_STATUS_3__REG_ADDR (0x03000360)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_STATUS_4__REG_OFFSET (0x00000164)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_STATUS_4__REG_ADDR (0x03000364)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_STATUS_5__REG_OFFSET (0x00000168)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_STATUS_5__REG_ADDR (0x03000368)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_STATUS_6__REG_OFFSET (0x0000016C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_STATUS_6__REG_ADDR (0x0300036C)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_STATUS_7__REG_OFFSET (0x00000170)
#define TT_CLUSTER_CTRL_T6_L1_CSR_WR_PORT_STATUS_7__REG_ADDR (0x03000370)
#define TT_CLUSTER_CTRL_DEBUG_SNOOP_REG_OFFSET (0x00000374)
#define TT_CLUSTER_CTRL_DEBUG_SNOOP_REG_ADDR (0x03000374)
#define TT_CLUSTER_CTRL_OVERLAY_INFO_REG_OFFSET (0x00000378)
#define TT_CLUSTER_CTRL_OVERLAY_INFO_REG_ADDR (0x03000378)
#define TT_CLUSTER_CTRL_SW_RAS_REG_OFFSET (0x0000037C)
#define TT_CLUSTER_CTRL_SW_RAS_REG_ADDR (0x0300037C)
#define TT_CLUSTER_CTRL_SBUS_RSINK_RESET_FALLBACK_REG_OFFSET (0x00000380)
#define TT_CLUSTER_CTRL_SBUS_RSINK_RESET_FALLBACK_REG_ADDR (0x03000380)

//==============================================================================
// Addresses for Address Map: tt_global_cmd_buf_cfg
//==============================================================================

#define TT_GLOBAL_CMD_BUF_CFG_REG_MAP_BASE_ADDR (0x03001000)
#define TT_GLOBAL_CMD_BUF_CFG_REG_MAP_SIZE (0x0000003C)

#define TT_GLOBAL_CMD_BUF_CFG_GLOBAL_CMD_BUF_READ_DATA_REG_OFFSET (0x00000000)
#define TT_GLOBAL_CMD_BUF_CFG_GLOBAL_CMD_BUF_READ_DATA_REG_ADDR (0x03001000)
#define TT_GLOBAL_CMD_BUF_CFG_GLOBAL_CMD_BUF_WRITE_DATA_REG_OFFSET (0x00000008)
#define TT_GLOBAL_CMD_BUF_CFG_GLOBAL_CMD_BUF_WRITE_DATA_REG_ADDR (0x03001008)
#define TT_GLOBAL_CMD_BUF_CFG_GLOBAL_CMD_BUF_SRC_ADDR_REG_OFFSET (0x00000010)
#define TT_GLOBAL_CMD_BUF_CFG_GLOBAL_CMD_BUF_SRC_ADDR_REG_ADDR (0x03001010)
#define TT_GLOBAL_CMD_BUF_CFG_GLOBAL_CMD_BUF_DEST_ADDR_REG_OFFSET (0x00000018)
#define TT_GLOBAL_CMD_BUF_CFG_GLOBAL_CMD_BUF_DEST_ADDR_REG_ADDR (0x03001018)
#define TT_GLOBAL_CMD_BUF_CFG_GLOBAL_CMD_BUF_COORD_REG_OFFSET (0x00000020)
#define TT_GLOBAL_CMD_BUF_CFG_GLOBAL_CMD_BUF_COORD_REG_ADDR (0x03001020)
#define TT_GLOBAL_CMD_BUF_CFG_GLOBAL_CMD_BUF_LEN_BYTES_REG_OFFSET (0x00000024)
#define TT_GLOBAL_CMD_BUF_CFG_GLOBAL_CMD_BUF_LEN_BYTES_REG_ADDR (0x03001024)
#define TT_GLOBAL_CMD_BUF_CFG_GLOBAL_CMD_BUF_REQ_VC_REG_OFFSET (0x00000028)
#define TT_GLOBAL_CMD_BUF_CFG_GLOBAL_CMD_BUF_REQ_VC_REG_ADDR (0x03001028)
#define TT_GLOBAL_CMD_BUF_CFG_GLOBAL_CMD_BUF_RESP_VC_REG_OFFSET (0x0000002C)
#define TT_GLOBAL_CMD_BUF_CFG_GLOBAL_CMD_BUF_RESP_VC_REG_ADDR (0x0300102C)
#define TT_GLOBAL_CMD_BUF_CFG_GLOBAL_CMD_BUF_TR_ID_REG_OFFSET (0x00000030)
#define TT_GLOBAL_CMD_BUF_CFG_GLOBAL_CMD_BUF_TR_ID_REG_ADDR (0x03001030)
#define TT_GLOBAL_CMD_BUF_CFG_GLOBAL_CMD_BUF_DEBUG_REG_OFFSET (0x00000034)
#define TT_GLOBAL_CMD_BUF_CFG_GLOBAL_CMD_BUF_DEBUG_REG_ADDR (0x03001034)
#define TT_GLOBAL_CMD_BUF_CFG_GLOBAL_CMD_BUF_MISC_REG_OFFSET (0x00000038)
#define TT_GLOBAL_CMD_BUF_CFG_GLOBAL_CMD_BUF_MISC_REG_ADDR (0x03001038)

//==============================================================================
// Addresses for Address Map: tt_idma_sideband
//==============================================================================

#define TT_IDMA_SIDEBAND_REG_MAP_BASE_ADDR (0x03002000)
#define TT_IDMA_SIDEBAND_REG_MAP_SIZE (0x00000138)

#define TT_IDMA_SIDEBAND_CONF_REG_OFFSET (0x00000000)
#define TT_IDMA_SIDEBAND_CONF_REG_ADDR (0x03002000)
#define TT_IDMA_SIDEBAND_STATUS_0__REG_OFFSET (0x00000004)
#define TT_IDMA_SIDEBAND_STATUS_0__REG_ADDR (0x03002004)
#define TT_IDMA_SIDEBAND_STATUS_1__REG_OFFSET (0x00000008)
#define TT_IDMA_SIDEBAND_STATUS_1__REG_ADDR (0x03002008)
#define TT_IDMA_SIDEBAND_STATUS_2__REG_OFFSET (0x0000000C)
#define TT_IDMA_SIDEBAND_STATUS_2__REG_ADDR (0x0300200C)
#define TT_IDMA_SIDEBAND_STATUS_3__REG_OFFSET (0x00000010)
#define TT_IDMA_SIDEBAND_STATUS_3__REG_ADDR (0x03002010)
#define TT_IDMA_SIDEBAND_STATUS_4__REG_OFFSET (0x00000014)
#define TT_IDMA_SIDEBAND_STATUS_4__REG_ADDR (0x03002014)
#define TT_IDMA_SIDEBAND_STATUS_5__REG_OFFSET (0x00000018)
#define TT_IDMA_SIDEBAND_STATUS_5__REG_ADDR (0x03002018)
#define TT_IDMA_SIDEBAND_STATUS_6__REG_OFFSET (0x0000001C)
#define TT_IDMA_SIDEBAND_STATUS_6__REG_ADDR (0x0300201C)
#define TT_IDMA_SIDEBAND_STATUS_7__REG_OFFSET (0x00000020)
#define TT_IDMA_SIDEBAND_STATUS_7__REG_ADDR (0x03002020)
#define TT_IDMA_SIDEBAND_STATUS_8__REG_OFFSET (0x00000024)
#define TT_IDMA_SIDEBAND_STATUS_8__REG_ADDR (0x03002024)
#define TT_IDMA_SIDEBAND_STATUS_9__REG_OFFSET (0x00000028)
#define TT_IDMA_SIDEBAND_STATUS_9__REG_ADDR (0x03002028)
#define TT_IDMA_SIDEBAND_STATUS_10__REG_OFFSET (0x0000002C)
#define TT_IDMA_SIDEBAND_STATUS_10__REG_ADDR (0x0300202C)
#define TT_IDMA_SIDEBAND_STATUS_11__REG_OFFSET (0x00000030)
#define TT_IDMA_SIDEBAND_STATUS_11__REG_ADDR (0x03002030)
#define TT_IDMA_SIDEBAND_STATUS_12__REG_OFFSET (0x00000034)
#define TT_IDMA_SIDEBAND_STATUS_12__REG_ADDR (0x03002034)
#define TT_IDMA_SIDEBAND_STATUS_13__REG_OFFSET (0x00000038)
#define TT_IDMA_SIDEBAND_STATUS_13__REG_ADDR (0x03002038)
#define TT_IDMA_SIDEBAND_STATUS_14__REG_OFFSET (0x0000003C)
#define TT_IDMA_SIDEBAND_STATUS_14__REG_ADDR (0x0300203C)
#define TT_IDMA_SIDEBAND_STATUS_15__REG_OFFSET (0x00000040)
#define TT_IDMA_SIDEBAND_STATUS_15__REG_ADDR (0x03002040)
#define TT_IDMA_SIDEBAND_NEXT_ID_0__REG_OFFSET (0x00000048)
#define TT_IDMA_SIDEBAND_NEXT_ID_0__REG_ADDR (0x03002048)
#define TT_IDMA_SIDEBAND_NEXT_ID_1__REG_OFFSET (0x00000050)
#define TT_IDMA_SIDEBAND_NEXT_ID_1__REG_ADDR (0x03002050)
#define TT_IDMA_SIDEBAND_NEXT_ID_2__REG_OFFSET (0x00000058)
#define TT_IDMA_SIDEBAND_NEXT_ID_2__REG_ADDR (0x03002058)
#define TT_IDMA_SIDEBAND_NEXT_ID_3__REG_OFFSET (0x00000060)
#define TT_IDMA_SIDEBAND_NEXT_ID_3__REG_ADDR (0x03002060)
#define TT_IDMA_SIDEBAND_NEXT_ID_4__REG_OFFSET (0x00000068)
#define TT_IDMA_SIDEBAND_NEXT_ID_4__REG_ADDR (0x03002068)
#define TT_IDMA_SIDEBAND_NEXT_ID_5__REG_OFFSET (0x00000070)
#define TT_IDMA_SIDEBAND_NEXT_ID_5__REG_ADDR (0x03002070)
#define TT_IDMA_SIDEBAND_NEXT_ID_6__REG_OFFSET (0x00000078)
#define TT_IDMA_SIDEBAND_NEXT_ID_6__REG_ADDR (0x03002078)
#define TT_IDMA_SIDEBAND_NEXT_ID_7__REG_OFFSET (0x00000080)
#define TT_IDMA_SIDEBAND_NEXT_ID_7__REG_ADDR (0x03002080)
#define TT_IDMA_SIDEBAND_NEXT_ID_8__REG_OFFSET (0x00000088)
#define TT_IDMA_SIDEBAND_NEXT_ID_8__REG_ADDR (0x03002088)
#define TT_IDMA_SIDEBAND_NEXT_ID_9__REG_OFFSET (0x00000090)
#define TT_IDMA_SIDEBAND_NEXT_ID_9__REG_ADDR (0x03002090)
#define TT_IDMA_SIDEBAND_NEXT_ID_10__REG_OFFSET (0x00000098)
#define TT_IDMA_SIDEBAND_NEXT_ID_10__REG_ADDR (0x03002098)
#define TT_IDMA_SIDEBAND_NEXT_ID_11__REG_OFFSET (0x000000A0)
#define TT_IDMA_SIDEBAND_NEXT_ID_11__REG_ADDR (0x030020A0)
#define TT_IDMA_SIDEBAND_NEXT_ID_12__REG_OFFSET (0x000000A8)
#define TT_IDMA_SIDEBAND_NEXT_ID_12__REG_ADDR (0x030020A8)
#define TT_IDMA_SIDEBAND_NEXT_ID_13__REG_OFFSET (0x000000B0)
#define TT_IDMA_SIDEBAND_NEXT_ID_13__REG_ADDR (0x030020B0)
#define TT_IDMA_SIDEBAND_NEXT_ID_14__REG_OFFSET (0x000000B8)
#define TT_IDMA_SIDEBAND_NEXT_ID_14__REG_ADDR (0x030020B8)
#define TT_IDMA_SIDEBAND_NEXT_ID_15__REG_OFFSET (0x000000C0)
#define TT_IDMA_SIDEBAND_NEXT_ID_15__REG_ADDR (0x030020C0)
#define TT_IDMA_SIDEBAND_DONE_ID_0__REG_OFFSET (0x000000C8)
#define TT_IDMA_SIDEBAND_DONE_ID_0__REG_ADDR (0x030020C8)
#define TT_IDMA_SIDEBAND_DONE_ID_1__REG_OFFSET (0x000000CC)
#define TT_IDMA_SIDEBAND_DONE_ID_1__REG_ADDR (0x030020CC)
#define TT_IDMA_SIDEBAND_DONE_ID_2__REG_OFFSET (0x000000D0)
#define TT_IDMA_SIDEBAND_DONE_ID_2__REG_ADDR (0x030020D0)
#define TT_IDMA_SIDEBAND_DONE_ID_3__REG_OFFSET (0x000000D4)
#define TT_IDMA_SIDEBAND_DONE_ID_3__REG_ADDR (0x030020D4)
#define TT_IDMA_SIDEBAND_DONE_ID_4__REG_OFFSET (0x000000D8)
#define TT_IDMA_SIDEBAND_DONE_ID_4__REG_ADDR (0x030020D8)
#define TT_IDMA_SIDEBAND_DONE_ID_5__REG_OFFSET (0x000000DC)
#define TT_IDMA_SIDEBAND_DONE_ID_5__REG_ADDR (0x030020DC)
#define TT_IDMA_SIDEBAND_DONE_ID_6__REG_OFFSET (0x000000E0)
#define TT_IDMA_SIDEBAND_DONE_ID_6__REG_ADDR (0x030020E0)
#define TT_IDMA_SIDEBAND_DONE_ID_7__REG_OFFSET (0x000000E4)
#define TT_IDMA_SIDEBAND_DONE_ID_7__REG_ADDR (0x030020E4)
#define TT_IDMA_SIDEBAND_DONE_ID_8__REG_OFFSET (0x000000E8)
#define TT_IDMA_SIDEBAND_DONE_ID_8__REG_ADDR (0x030020E8)
#define TT_IDMA_SIDEBAND_DONE_ID_9__REG_OFFSET (0x000000EC)
#define TT_IDMA_SIDEBAND_DONE_ID_9__REG_ADDR (0x030020EC)
#define TT_IDMA_SIDEBAND_DONE_ID_10__REG_OFFSET (0x000000F0)
#define TT_IDMA_SIDEBAND_DONE_ID_10__REG_ADDR (0x030020F0)
#define TT_IDMA_SIDEBAND_DONE_ID_11__REG_OFFSET (0x000000F4)
#define TT_IDMA_SIDEBAND_DONE_ID_11__REG_ADDR (0x030020F4)
#define TT_IDMA_SIDEBAND_DONE_ID_12__REG_OFFSET (0x000000F8)
#define TT_IDMA_SIDEBAND_DONE_ID_12__REG_ADDR (0x030020F8)
#define TT_IDMA_SIDEBAND_DONE_ID_13__REG_OFFSET (0x000000FC)
#define TT_IDMA_SIDEBAND_DONE_ID_13__REG_ADDR (0x030020FC)
#define TT_IDMA_SIDEBAND_DONE_ID_14__REG_OFFSET (0x00000100)
#define TT_IDMA_SIDEBAND_DONE_ID_14__REG_ADDR (0x03002100)
#define TT_IDMA_SIDEBAND_DONE_ID_15__REG_OFFSET (0x00000104)
#define TT_IDMA_SIDEBAND_DONE_ID_15__REG_ADDR (0x03002104)
#define TT_IDMA_SIDEBAND_DST_ADDR_LOW_REG_OFFSET (0x00000108)
#define TT_IDMA_SIDEBAND_DST_ADDR_LOW_REG_ADDR (0x03002108)
#define TT_IDMA_SIDEBAND_DST_ADDR_HIGH_REG_OFFSET (0x0000010C)
#define TT_IDMA_SIDEBAND_DST_ADDR_HIGH_REG_ADDR (0x0300210C)
#define TT_IDMA_SIDEBAND_SRC_ADDR_LOW_REG_OFFSET (0x00000110)
#define TT_IDMA_SIDEBAND_SRC_ADDR_LOW_REG_ADDR (0x03002110)
#define TT_IDMA_SIDEBAND_SRC_ADDR_HIGH_REG_OFFSET (0x00000114)
#define TT_IDMA_SIDEBAND_SRC_ADDR_HIGH_REG_ADDR (0x03002114)
#define TT_IDMA_SIDEBAND_LENGTH_LOW_REG_OFFSET (0x00000118)
#define TT_IDMA_SIDEBAND_LENGTH_LOW_REG_ADDR (0x03002118)
#define TT_IDMA_SIDEBAND_LENGTH_HIGH_REG_OFFSET (0x0000011C)
#define TT_IDMA_SIDEBAND_LENGTH_HIGH_REG_ADDR (0x0300211C)
#define TT_IDMA_SIDEBAND_DST_STRIDE_2_LOW_REG_OFFSET (0x00000120)
#define TT_IDMA_SIDEBAND_DST_STRIDE_2_LOW_REG_ADDR (0x03002120)
#define TT_IDMA_SIDEBAND_DST_STRIDE_2_HIGH_REG_OFFSET (0x00000124)
#define TT_IDMA_SIDEBAND_DST_STRIDE_2_HIGH_REG_ADDR (0x03002124)
#define TT_IDMA_SIDEBAND_SRC_STRIDE_2_LOW_REG_OFFSET (0x00000128)
#define TT_IDMA_SIDEBAND_SRC_STRIDE_2_LOW_REG_ADDR (0x03002128)
#define TT_IDMA_SIDEBAND_SRC_STRIDE_2_HIGH_REG_OFFSET (0x0000012C)
#define TT_IDMA_SIDEBAND_SRC_STRIDE_2_HIGH_REG_ADDR (0x0300212C)
#define TT_IDMA_SIDEBAND_REPS_2_LOW_REG_OFFSET (0x00000130)
#define TT_IDMA_SIDEBAND_REPS_2_LOW_REG_ADDR (0x03002130)
#define TT_IDMA_SIDEBAND_REPS_2_HIGH_REG_OFFSET (0x00000134)
#define TT_IDMA_SIDEBAND_REPS_2_HIGH_REG_ADDR (0x03002134)

//==============================================================================
// Addresses for Address Map: tt_overlay_llk_tile_counters
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_REG_MAP_BASE_ADDR (0x03003000)
#define TT_OVERLAY_LLK_TILE_COUNTERS_REG_MAP_SIZE (0x00000800)

//==============================================================================
// Addresses for Address Map: tt_llk_interface
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_REG_MAP_BASE_ADDR (0x03003000)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_REG_MAP_SIZE (0x00000200)

//==============================================================================
// Register File: tile_counters_0_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_0__REG_FILE_BASE_ADDR (0x03003000)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_0__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_0__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_0__RESET_REG_ADDR (0x03003004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_0__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_0__POSTED_REG_ADDR (0x03003008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_0__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_0__ACKED_REG_ADDR (0x0300300C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_0__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_0__BUFFER_CAPACITY_REG_ADDR (0x03003010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_0__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_0__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_0__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_0__TILES_FREE_THRESHOLD_REG_ADDR (0x0300301C)

//==============================================================================
// Register File: tile_counters_1_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_1__REG_FILE_BASE_ADDR (0x03003020)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_1__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_1__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_1__RESET_REG_ADDR (0x03003024)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_1__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_1__POSTED_REG_ADDR (0x03003028)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_1__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_1__ACKED_REG_ADDR (0x0300302C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_1__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_1__BUFFER_CAPACITY_REG_ADDR (0x03003030)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_1__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_1__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003038)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_1__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_1__TILES_FREE_THRESHOLD_REG_ADDR (0x0300303C)

//==============================================================================
// Register File: tile_counters_2_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_2__REG_FILE_BASE_ADDR (0x03003040)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_2__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_2__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_2__RESET_REG_ADDR (0x03003044)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_2__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_2__POSTED_REG_ADDR (0x03003048)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_2__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_2__ACKED_REG_ADDR (0x0300304C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_2__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_2__BUFFER_CAPACITY_REG_ADDR (0x03003050)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_2__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_2__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003058)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_2__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_2__TILES_FREE_THRESHOLD_REG_ADDR (0x0300305C)

//==============================================================================
// Register File: tile_counters_3_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_3__REG_FILE_BASE_ADDR (0x03003060)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_3__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_3__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_3__RESET_REG_ADDR (0x03003064)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_3__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_3__POSTED_REG_ADDR (0x03003068)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_3__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_3__ACKED_REG_ADDR (0x0300306C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_3__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_3__BUFFER_CAPACITY_REG_ADDR (0x03003070)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_3__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_3__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003078)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_3__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_3__TILES_FREE_THRESHOLD_REG_ADDR (0x0300307C)

//==============================================================================
// Register File: tile_counters_4_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_4__REG_FILE_BASE_ADDR (0x03003080)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_4__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_4__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_4__RESET_REG_ADDR (0x03003084)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_4__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_4__POSTED_REG_ADDR (0x03003088)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_4__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_4__ACKED_REG_ADDR (0x0300308C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_4__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_4__BUFFER_CAPACITY_REG_ADDR (0x03003090)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_4__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_4__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003098)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_4__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_4__TILES_FREE_THRESHOLD_REG_ADDR (0x0300309C)

//==============================================================================
// Register File: tile_counters_5_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_5__REG_FILE_BASE_ADDR (0x030030A0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_5__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_5__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_5__RESET_REG_ADDR (0x030030A4)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_5__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_5__POSTED_REG_ADDR (0x030030A8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_5__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_5__ACKED_REG_ADDR (0x030030AC)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_5__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_5__BUFFER_CAPACITY_REG_ADDR (0x030030B0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_5__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_5__TILES_AVAIL_THRESHOLD_REG_ADDR (0x030030B8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_5__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_5__TILES_FREE_THRESHOLD_REG_ADDR (0x030030BC)

//==============================================================================
// Register File: tile_counters_6_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_6__REG_FILE_BASE_ADDR (0x030030C0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_6__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_6__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_6__RESET_REG_ADDR (0x030030C4)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_6__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_6__POSTED_REG_ADDR (0x030030C8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_6__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_6__ACKED_REG_ADDR (0x030030CC)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_6__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_6__BUFFER_CAPACITY_REG_ADDR (0x030030D0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_6__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_6__TILES_AVAIL_THRESHOLD_REG_ADDR (0x030030D8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_6__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_6__TILES_FREE_THRESHOLD_REG_ADDR (0x030030DC)

//==============================================================================
// Register File: tile_counters_7_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_7__REG_FILE_BASE_ADDR (0x030030E0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_7__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_7__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_7__RESET_REG_ADDR (0x030030E4)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_7__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_7__POSTED_REG_ADDR (0x030030E8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_7__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_7__ACKED_REG_ADDR (0x030030EC)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_7__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_7__BUFFER_CAPACITY_REG_ADDR (0x030030F0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_7__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_7__TILES_AVAIL_THRESHOLD_REG_ADDR (0x030030F8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_7__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_7__TILES_FREE_THRESHOLD_REG_ADDR (0x030030FC)

//==============================================================================
// Register File: tile_counters_8_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_8__REG_FILE_BASE_ADDR (0x03003100)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_8__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_8__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_8__RESET_REG_ADDR (0x03003104)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_8__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_8__POSTED_REG_ADDR (0x03003108)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_8__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_8__ACKED_REG_ADDR (0x0300310C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_8__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_8__BUFFER_CAPACITY_REG_ADDR (0x03003110)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_8__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_8__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003118)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_8__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_8__TILES_FREE_THRESHOLD_REG_ADDR (0x0300311C)

//==============================================================================
// Register File: tile_counters_9_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_9__REG_FILE_BASE_ADDR (0x03003120)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_9__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_9__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_9__RESET_REG_ADDR (0x03003124)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_9__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_9__POSTED_REG_ADDR (0x03003128)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_9__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_9__ACKED_REG_ADDR (0x0300312C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_9__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_9__BUFFER_CAPACITY_REG_ADDR (0x03003130)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_9__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_9__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003138)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_9__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_9__TILES_FREE_THRESHOLD_REG_ADDR (0x0300313C)

//==============================================================================
// Register File: tile_counters_10_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_10__REG_FILE_BASE_ADDR (0x03003140)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_10__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_10__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_10__RESET_REG_ADDR (0x03003144)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_10__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_10__POSTED_REG_ADDR (0x03003148)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_10__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_10__ACKED_REG_ADDR (0x0300314C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_10__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_10__BUFFER_CAPACITY_REG_ADDR (0x03003150)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_10__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_10__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003158)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_10__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_10__TILES_FREE_THRESHOLD_REG_ADDR (0x0300315C)

//==============================================================================
// Register File: tile_counters_11_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_11__REG_FILE_BASE_ADDR (0x03003160)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_11__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_11__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_11__RESET_REG_ADDR (0x03003164)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_11__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_11__POSTED_REG_ADDR (0x03003168)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_11__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_11__ACKED_REG_ADDR (0x0300316C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_11__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_11__BUFFER_CAPACITY_REG_ADDR (0x03003170)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_11__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_11__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003178)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_11__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_11__TILES_FREE_THRESHOLD_REG_ADDR (0x0300317C)

//==============================================================================
// Register File: tile_counters_12_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_12__REG_FILE_BASE_ADDR (0x03003180)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_12__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_12__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_12__RESET_REG_ADDR (0x03003184)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_12__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_12__POSTED_REG_ADDR (0x03003188)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_12__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_12__ACKED_REG_ADDR (0x0300318C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_12__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_12__BUFFER_CAPACITY_REG_ADDR (0x03003190)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_12__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_12__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003198)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_12__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_12__TILES_FREE_THRESHOLD_REG_ADDR (0x0300319C)

//==============================================================================
// Register File: tile_counters_13_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_13__REG_FILE_BASE_ADDR (0x030031A0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_13__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_13__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_13__RESET_REG_ADDR (0x030031A4)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_13__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_13__POSTED_REG_ADDR (0x030031A8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_13__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_13__ACKED_REG_ADDR (0x030031AC)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_13__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_13__BUFFER_CAPACITY_REG_ADDR (0x030031B0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_13__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_13__TILES_AVAIL_THRESHOLD_REG_ADDR (0x030031B8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_13__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_13__TILES_FREE_THRESHOLD_REG_ADDR (0x030031BC)

//==============================================================================
// Register File: tile_counters_14_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_14__REG_FILE_BASE_ADDR (0x030031C0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_14__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_14__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_14__RESET_REG_ADDR (0x030031C4)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_14__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_14__POSTED_REG_ADDR (0x030031C8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_14__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_14__ACKED_REG_ADDR (0x030031CC)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_14__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_14__BUFFER_CAPACITY_REG_ADDR (0x030031D0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_14__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_14__TILES_AVAIL_THRESHOLD_REG_ADDR (0x030031D8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_14__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_14__TILES_FREE_THRESHOLD_REG_ADDR (0x030031DC)

//==============================================================================
// Register File: tile_counters_15_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_15__REG_FILE_BASE_ADDR (0x030031E0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_15__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_15__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_15__RESET_REG_ADDR (0x030031E4)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_15__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_15__POSTED_REG_ADDR (0x030031E8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_15__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_15__ACKED_REG_ADDR (0x030031EC)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_15__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_15__BUFFER_CAPACITY_REG_ADDR (0x030031F0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_15__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_15__TILES_AVAIL_THRESHOLD_REG_ADDR (0x030031F8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_15__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_TILE_COUNTERS_15__TILES_FREE_THRESHOLD_REG_ADDR (0x030031FC)

//==============================================================================
// Addresses for Address Map: tt_llk_interface_1
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_REG_MAP_BASE_ADDR (0x03003200)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_REG_MAP_SIZE (0x00000200)

//==============================================================================
// Register File: tile_counters_0_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_0__REG_FILE_BASE_ADDR (0x03003200)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_0__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_0__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_0__RESET_REG_ADDR (0x03003204)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_0__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_0__POSTED_REG_ADDR (0x03003208)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_0__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_0__ACKED_REG_ADDR (0x0300320C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_0__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_0__BUFFER_CAPACITY_REG_ADDR (0x03003210)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_0__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_0__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003218)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_0__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_0__TILES_FREE_THRESHOLD_REG_ADDR (0x0300321C)

//==============================================================================
// Register File: tile_counters_1_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_1__REG_FILE_BASE_ADDR (0x03003220)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_1__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_1__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_1__RESET_REG_ADDR (0x03003224)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_1__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_1__POSTED_REG_ADDR (0x03003228)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_1__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_1__ACKED_REG_ADDR (0x0300322C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_1__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_1__BUFFER_CAPACITY_REG_ADDR (0x03003230)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_1__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_1__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003238)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_1__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_1__TILES_FREE_THRESHOLD_REG_ADDR (0x0300323C)

//==============================================================================
// Register File: tile_counters_2_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_2__REG_FILE_BASE_ADDR (0x03003240)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_2__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_2__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_2__RESET_REG_ADDR (0x03003244)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_2__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_2__POSTED_REG_ADDR (0x03003248)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_2__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_2__ACKED_REG_ADDR (0x0300324C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_2__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_2__BUFFER_CAPACITY_REG_ADDR (0x03003250)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_2__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_2__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003258)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_2__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_2__TILES_FREE_THRESHOLD_REG_ADDR (0x0300325C)

//==============================================================================
// Register File: tile_counters_3_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_3__REG_FILE_BASE_ADDR (0x03003260)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_3__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_3__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_3__RESET_REG_ADDR (0x03003264)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_3__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_3__POSTED_REG_ADDR (0x03003268)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_3__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_3__ACKED_REG_ADDR (0x0300326C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_3__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_3__BUFFER_CAPACITY_REG_ADDR (0x03003270)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_3__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_3__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003278)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_3__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_3__TILES_FREE_THRESHOLD_REG_ADDR (0x0300327C)

//==============================================================================
// Register File: tile_counters_4_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_4__REG_FILE_BASE_ADDR (0x03003280)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_4__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_4__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_4__RESET_REG_ADDR (0x03003284)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_4__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_4__POSTED_REG_ADDR (0x03003288)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_4__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_4__ACKED_REG_ADDR (0x0300328C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_4__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_4__BUFFER_CAPACITY_REG_ADDR (0x03003290)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_4__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_4__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003298)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_4__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_4__TILES_FREE_THRESHOLD_REG_ADDR (0x0300329C)

//==============================================================================
// Register File: tile_counters_5_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_5__REG_FILE_BASE_ADDR (0x030032A0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_5__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_5__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_5__RESET_REG_ADDR (0x030032A4)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_5__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_5__POSTED_REG_ADDR (0x030032A8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_5__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_5__ACKED_REG_ADDR (0x030032AC)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_5__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_5__BUFFER_CAPACITY_REG_ADDR (0x030032B0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_5__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_5__TILES_AVAIL_THRESHOLD_REG_ADDR (0x030032B8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_5__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_5__TILES_FREE_THRESHOLD_REG_ADDR (0x030032BC)

//==============================================================================
// Register File: tile_counters_6_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_6__REG_FILE_BASE_ADDR (0x030032C0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_6__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_6__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_6__RESET_REG_ADDR (0x030032C4)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_6__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_6__POSTED_REG_ADDR (0x030032C8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_6__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_6__ACKED_REG_ADDR (0x030032CC)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_6__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_6__BUFFER_CAPACITY_REG_ADDR (0x030032D0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_6__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_6__TILES_AVAIL_THRESHOLD_REG_ADDR (0x030032D8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_6__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_6__TILES_FREE_THRESHOLD_REG_ADDR (0x030032DC)

//==============================================================================
// Register File: tile_counters_7_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_7__REG_FILE_BASE_ADDR (0x030032E0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_7__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_7__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_7__RESET_REG_ADDR (0x030032E4)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_7__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_7__POSTED_REG_ADDR (0x030032E8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_7__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_7__ACKED_REG_ADDR (0x030032EC)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_7__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_7__BUFFER_CAPACITY_REG_ADDR (0x030032F0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_7__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_7__TILES_AVAIL_THRESHOLD_REG_ADDR (0x030032F8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_7__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_7__TILES_FREE_THRESHOLD_REG_ADDR (0x030032FC)

//==============================================================================
// Register File: tile_counters_8_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_8__REG_FILE_BASE_ADDR (0x03003300)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_8__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_8__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_8__RESET_REG_ADDR (0x03003304)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_8__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_8__POSTED_REG_ADDR (0x03003308)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_8__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_8__ACKED_REG_ADDR (0x0300330C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_8__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_8__BUFFER_CAPACITY_REG_ADDR (0x03003310)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_8__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_8__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003318)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_8__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_8__TILES_FREE_THRESHOLD_REG_ADDR (0x0300331C)

//==============================================================================
// Register File: tile_counters_9_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_9__REG_FILE_BASE_ADDR (0x03003320)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_9__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_9__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_9__RESET_REG_ADDR (0x03003324)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_9__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_9__POSTED_REG_ADDR (0x03003328)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_9__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_9__ACKED_REG_ADDR (0x0300332C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_9__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_9__BUFFER_CAPACITY_REG_ADDR (0x03003330)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_9__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_9__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003338)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_9__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_9__TILES_FREE_THRESHOLD_REG_ADDR (0x0300333C)

//==============================================================================
// Register File: tile_counters_10_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_10__REG_FILE_BASE_ADDR (0x03003340)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_10__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_10__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_10__RESET_REG_ADDR (0x03003344)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_10__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_10__POSTED_REG_ADDR (0x03003348)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_10__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_10__ACKED_REG_ADDR (0x0300334C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_10__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_10__BUFFER_CAPACITY_REG_ADDR (0x03003350)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_10__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_10__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003358)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_10__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_10__TILES_FREE_THRESHOLD_REG_ADDR (0x0300335C)

//==============================================================================
// Register File: tile_counters_11_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_11__REG_FILE_BASE_ADDR (0x03003360)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_11__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_11__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_11__RESET_REG_ADDR (0x03003364)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_11__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_11__POSTED_REG_ADDR (0x03003368)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_11__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_11__ACKED_REG_ADDR (0x0300336C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_11__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_11__BUFFER_CAPACITY_REG_ADDR (0x03003370)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_11__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_11__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003378)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_11__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_11__TILES_FREE_THRESHOLD_REG_ADDR (0x0300337C)

//==============================================================================
// Register File: tile_counters_12_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_12__REG_FILE_BASE_ADDR (0x03003380)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_12__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_12__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_12__RESET_REG_ADDR (0x03003384)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_12__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_12__POSTED_REG_ADDR (0x03003388)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_12__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_12__ACKED_REG_ADDR (0x0300338C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_12__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_12__BUFFER_CAPACITY_REG_ADDR (0x03003390)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_12__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_12__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003398)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_12__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_12__TILES_FREE_THRESHOLD_REG_ADDR (0x0300339C)

//==============================================================================
// Register File: tile_counters_13_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_13__REG_FILE_BASE_ADDR (0x030033A0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_13__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_13__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_13__RESET_REG_ADDR (0x030033A4)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_13__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_13__POSTED_REG_ADDR (0x030033A8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_13__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_13__ACKED_REG_ADDR (0x030033AC)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_13__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_13__BUFFER_CAPACITY_REG_ADDR (0x030033B0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_13__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_13__TILES_AVAIL_THRESHOLD_REG_ADDR (0x030033B8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_13__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_13__TILES_FREE_THRESHOLD_REG_ADDR (0x030033BC)

//==============================================================================
// Register File: tile_counters_14_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_14__REG_FILE_BASE_ADDR (0x030033C0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_14__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_14__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_14__RESET_REG_ADDR (0x030033C4)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_14__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_14__POSTED_REG_ADDR (0x030033C8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_14__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_14__ACKED_REG_ADDR (0x030033CC)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_14__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_14__BUFFER_CAPACITY_REG_ADDR (0x030033D0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_14__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_14__TILES_AVAIL_THRESHOLD_REG_ADDR (0x030033D8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_14__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_14__TILES_FREE_THRESHOLD_REG_ADDR (0x030033DC)

//==============================================================================
// Register File: tile_counters_15_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_15__REG_FILE_BASE_ADDR (0x030033E0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_15__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_15__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_15__RESET_REG_ADDR (0x030033E4)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_15__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_15__POSTED_REG_ADDR (0x030033E8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_15__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_15__ACKED_REG_ADDR (0x030033EC)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_15__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_15__BUFFER_CAPACITY_REG_ADDR (0x030033F0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_15__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_15__TILES_AVAIL_THRESHOLD_REG_ADDR (0x030033F8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_15__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_1_TILE_COUNTERS_15__TILES_FREE_THRESHOLD_REG_ADDR (0x030033FC)

//==============================================================================
// Addresses for Address Map: tt_llk_interface_2
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_REG_MAP_BASE_ADDR (0x03003400)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_REG_MAP_SIZE (0x00000200)

//==============================================================================
// Register File: tile_counters_0_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_0__REG_FILE_BASE_ADDR (0x03003400)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_0__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_0__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_0__RESET_REG_ADDR (0x03003404)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_0__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_0__POSTED_REG_ADDR (0x03003408)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_0__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_0__ACKED_REG_ADDR (0x0300340C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_0__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_0__BUFFER_CAPACITY_REG_ADDR (0x03003410)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_0__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_0__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003418)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_0__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_0__TILES_FREE_THRESHOLD_REG_ADDR (0x0300341C)

//==============================================================================
// Register File: tile_counters_1_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_1__REG_FILE_BASE_ADDR (0x03003420)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_1__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_1__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_1__RESET_REG_ADDR (0x03003424)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_1__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_1__POSTED_REG_ADDR (0x03003428)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_1__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_1__ACKED_REG_ADDR (0x0300342C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_1__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_1__BUFFER_CAPACITY_REG_ADDR (0x03003430)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_1__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_1__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003438)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_1__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_1__TILES_FREE_THRESHOLD_REG_ADDR (0x0300343C)

//==============================================================================
// Register File: tile_counters_2_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_2__REG_FILE_BASE_ADDR (0x03003440)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_2__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_2__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_2__RESET_REG_ADDR (0x03003444)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_2__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_2__POSTED_REG_ADDR (0x03003448)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_2__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_2__ACKED_REG_ADDR (0x0300344C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_2__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_2__BUFFER_CAPACITY_REG_ADDR (0x03003450)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_2__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_2__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003458)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_2__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_2__TILES_FREE_THRESHOLD_REG_ADDR (0x0300345C)

//==============================================================================
// Register File: tile_counters_3_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_3__REG_FILE_BASE_ADDR (0x03003460)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_3__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_3__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_3__RESET_REG_ADDR (0x03003464)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_3__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_3__POSTED_REG_ADDR (0x03003468)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_3__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_3__ACKED_REG_ADDR (0x0300346C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_3__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_3__BUFFER_CAPACITY_REG_ADDR (0x03003470)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_3__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_3__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003478)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_3__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_3__TILES_FREE_THRESHOLD_REG_ADDR (0x0300347C)

//==============================================================================
// Register File: tile_counters_4_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_4__REG_FILE_BASE_ADDR (0x03003480)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_4__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_4__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_4__RESET_REG_ADDR (0x03003484)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_4__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_4__POSTED_REG_ADDR (0x03003488)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_4__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_4__ACKED_REG_ADDR (0x0300348C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_4__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_4__BUFFER_CAPACITY_REG_ADDR (0x03003490)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_4__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_4__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003498)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_4__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_4__TILES_FREE_THRESHOLD_REG_ADDR (0x0300349C)

//==============================================================================
// Register File: tile_counters_5_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_5__REG_FILE_BASE_ADDR (0x030034A0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_5__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_5__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_5__RESET_REG_ADDR (0x030034A4)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_5__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_5__POSTED_REG_ADDR (0x030034A8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_5__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_5__ACKED_REG_ADDR (0x030034AC)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_5__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_5__BUFFER_CAPACITY_REG_ADDR (0x030034B0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_5__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_5__TILES_AVAIL_THRESHOLD_REG_ADDR (0x030034B8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_5__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_5__TILES_FREE_THRESHOLD_REG_ADDR (0x030034BC)

//==============================================================================
// Register File: tile_counters_6_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_6__REG_FILE_BASE_ADDR (0x030034C0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_6__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_6__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_6__RESET_REG_ADDR (0x030034C4)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_6__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_6__POSTED_REG_ADDR (0x030034C8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_6__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_6__ACKED_REG_ADDR (0x030034CC)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_6__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_6__BUFFER_CAPACITY_REG_ADDR (0x030034D0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_6__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_6__TILES_AVAIL_THRESHOLD_REG_ADDR (0x030034D8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_6__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_6__TILES_FREE_THRESHOLD_REG_ADDR (0x030034DC)

//==============================================================================
// Register File: tile_counters_7_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_7__REG_FILE_BASE_ADDR (0x030034E0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_7__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_7__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_7__RESET_REG_ADDR (0x030034E4)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_7__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_7__POSTED_REG_ADDR (0x030034E8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_7__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_7__ACKED_REG_ADDR (0x030034EC)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_7__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_7__BUFFER_CAPACITY_REG_ADDR (0x030034F0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_7__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_7__TILES_AVAIL_THRESHOLD_REG_ADDR (0x030034F8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_7__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_7__TILES_FREE_THRESHOLD_REG_ADDR (0x030034FC)

//==============================================================================
// Register File: tile_counters_8_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_8__REG_FILE_BASE_ADDR (0x03003500)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_8__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_8__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_8__RESET_REG_ADDR (0x03003504)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_8__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_8__POSTED_REG_ADDR (0x03003508)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_8__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_8__ACKED_REG_ADDR (0x0300350C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_8__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_8__BUFFER_CAPACITY_REG_ADDR (0x03003510)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_8__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_8__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003518)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_8__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_8__TILES_FREE_THRESHOLD_REG_ADDR (0x0300351C)

//==============================================================================
// Register File: tile_counters_9_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_9__REG_FILE_BASE_ADDR (0x03003520)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_9__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_9__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_9__RESET_REG_ADDR (0x03003524)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_9__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_9__POSTED_REG_ADDR (0x03003528)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_9__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_9__ACKED_REG_ADDR (0x0300352C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_9__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_9__BUFFER_CAPACITY_REG_ADDR (0x03003530)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_9__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_9__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003538)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_9__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_9__TILES_FREE_THRESHOLD_REG_ADDR (0x0300353C)

//==============================================================================
// Register File: tile_counters_10_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_10__REG_FILE_BASE_ADDR (0x03003540)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_10__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_10__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_10__RESET_REG_ADDR (0x03003544)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_10__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_10__POSTED_REG_ADDR (0x03003548)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_10__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_10__ACKED_REG_ADDR (0x0300354C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_10__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_10__BUFFER_CAPACITY_REG_ADDR (0x03003550)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_10__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_10__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003558)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_10__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_10__TILES_FREE_THRESHOLD_REG_ADDR (0x0300355C)

//==============================================================================
// Register File: tile_counters_11_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_11__REG_FILE_BASE_ADDR (0x03003560)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_11__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_11__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_11__RESET_REG_ADDR (0x03003564)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_11__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_11__POSTED_REG_ADDR (0x03003568)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_11__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_11__ACKED_REG_ADDR (0x0300356C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_11__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_11__BUFFER_CAPACITY_REG_ADDR (0x03003570)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_11__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_11__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003578)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_11__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_11__TILES_FREE_THRESHOLD_REG_ADDR (0x0300357C)

//==============================================================================
// Register File: tile_counters_12_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_12__REG_FILE_BASE_ADDR (0x03003580)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_12__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_12__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_12__RESET_REG_ADDR (0x03003584)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_12__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_12__POSTED_REG_ADDR (0x03003588)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_12__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_12__ACKED_REG_ADDR (0x0300358C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_12__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_12__BUFFER_CAPACITY_REG_ADDR (0x03003590)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_12__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_12__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003598)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_12__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_12__TILES_FREE_THRESHOLD_REG_ADDR (0x0300359C)

//==============================================================================
// Register File: tile_counters_13_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_13__REG_FILE_BASE_ADDR (0x030035A0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_13__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_13__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_13__RESET_REG_ADDR (0x030035A4)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_13__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_13__POSTED_REG_ADDR (0x030035A8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_13__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_13__ACKED_REG_ADDR (0x030035AC)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_13__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_13__BUFFER_CAPACITY_REG_ADDR (0x030035B0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_13__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_13__TILES_AVAIL_THRESHOLD_REG_ADDR (0x030035B8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_13__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_13__TILES_FREE_THRESHOLD_REG_ADDR (0x030035BC)

//==============================================================================
// Register File: tile_counters_14_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_14__REG_FILE_BASE_ADDR (0x030035C0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_14__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_14__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_14__RESET_REG_ADDR (0x030035C4)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_14__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_14__POSTED_REG_ADDR (0x030035C8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_14__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_14__ACKED_REG_ADDR (0x030035CC)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_14__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_14__BUFFER_CAPACITY_REG_ADDR (0x030035D0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_14__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_14__TILES_AVAIL_THRESHOLD_REG_ADDR (0x030035D8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_14__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_14__TILES_FREE_THRESHOLD_REG_ADDR (0x030035DC)

//==============================================================================
// Register File: tile_counters_15_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_15__REG_FILE_BASE_ADDR (0x030035E0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_15__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_15__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_15__RESET_REG_ADDR (0x030035E4)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_15__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_15__POSTED_REG_ADDR (0x030035E8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_15__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_15__ACKED_REG_ADDR (0x030035EC)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_15__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_15__BUFFER_CAPACITY_REG_ADDR (0x030035F0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_15__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_15__TILES_AVAIL_THRESHOLD_REG_ADDR (0x030035F8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_15__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_2_TILE_COUNTERS_15__TILES_FREE_THRESHOLD_REG_ADDR (0x030035FC)

//==============================================================================
// Addresses for Address Map: tt_llk_interface_3
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_REG_MAP_BASE_ADDR (0x03003600)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_REG_MAP_SIZE (0x00000200)

//==============================================================================
// Register File: tile_counters_0_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_0__REG_FILE_BASE_ADDR (0x03003600)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_0__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_0__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_0__RESET_REG_ADDR (0x03003604)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_0__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_0__POSTED_REG_ADDR (0x03003608)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_0__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_0__ACKED_REG_ADDR (0x0300360C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_0__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_0__BUFFER_CAPACITY_REG_ADDR (0x03003610)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_0__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_0__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003618)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_0__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_0__TILES_FREE_THRESHOLD_REG_ADDR (0x0300361C)

//==============================================================================
// Register File: tile_counters_1_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_1__REG_FILE_BASE_ADDR (0x03003620)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_1__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_1__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_1__RESET_REG_ADDR (0x03003624)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_1__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_1__POSTED_REG_ADDR (0x03003628)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_1__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_1__ACKED_REG_ADDR (0x0300362C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_1__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_1__BUFFER_CAPACITY_REG_ADDR (0x03003630)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_1__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_1__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003638)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_1__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_1__TILES_FREE_THRESHOLD_REG_ADDR (0x0300363C)

//==============================================================================
// Register File: tile_counters_2_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_2__REG_FILE_BASE_ADDR (0x03003640)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_2__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_2__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_2__RESET_REG_ADDR (0x03003644)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_2__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_2__POSTED_REG_ADDR (0x03003648)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_2__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_2__ACKED_REG_ADDR (0x0300364C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_2__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_2__BUFFER_CAPACITY_REG_ADDR (0x03003650)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_2__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_2__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003658)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_2__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_2__TILES_FREE_THRESHOLD_REG_ADDR (0x0300365C)

//==============================================================================
// Register File: tile_counters_3_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_3__REG_FILE_BASE_ADDR (0x03003660)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_3__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_3__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_3__RESET_REG_ADDR (0x03003664)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_3__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_3__POSTED_REG_ADDR (0x03003668)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_3__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_3__ACKED_REG_ADDR (0x0300366C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_3__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_3__BUFFER_CAPACITY_REG_ADDR (0x03003670)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_3__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_3__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003678)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_3__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_3__TILES_FREE_THRESHOLD_REG_ADDR (0x0300367C)

//==============================================================================
// Register File: tile_counters_4_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_4__REG_FILE_BASE_ADDR (0x03003680)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_4__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_4__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_4__RESET_REG_ADDR (0x03003684)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_4__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_4__POSTED_REG_ADDR (0x03003688)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_4__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_4__ACKED_REG_ADDR (0x0300368C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_4__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_4__BUFFER_CAPACITY_REG_ADDR (0x03003690)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_4__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_4__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003698)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_4__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_4__TILES_FREE_THRESHOLD_REG_ADDR (0x0300369C)

//==============================================================================
// Register File: tile_counters_5_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_5__REG_FILE_BASE_ADDR (0x030036A0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_5__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_5__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_5__RESET_REG_ADDR (0x030036A4)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_5__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_5__POSTED_REG_ADDR (0x030036A8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_5__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_5__ACKED_REG_ADDR (0x030036AC)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_5__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_5__BUFFER_CAPACITY_REG_ADDR (0x030036B0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_5__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_5__TILES_AVAIL_THRESHOLD_REG_ADDR (0x030036B8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_5__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_5__TILES_FREE_THRESHOLD_REG_ADDR (0x030036BC)

//==============================================================================
// Register File: tile_counters_6_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_6__REG_FILE_BASE_ADDR (0x030036C0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_6__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_6__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_6__RESET_REG_ADDR (0x030036C4)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_6__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_6__POSTED_REG_ADDR (0x030036C8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_6__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_6__ACKED_REG_ADDR (0x030036CC)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_6__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_6__BUFFER_CAPACITY_REG_ADDR (0x030036D0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_6__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_6__TILES_AVAIL_THRESHOLD_REG_ADDR (0x030036D8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_6__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_6__TILES_FREE_THRESHOLD_REG_ADDR (0x030036DC)

//==============================================================================
// Register File: tile_counters_7_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_7__REG_FILE_BASE_ADDR (0x030036E0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_7__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_7__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_7__RESET_REG_ADDR (0x030036E4)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_7__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_7__POSTED_REG_ADDR (0x030036E8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_7__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_7__ACKED_REG_ADDR (0x030036EC)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_7__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_7__BUFFER_CAPACITY_REG_ADDR (0x030036F0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_7__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_7__TILES_AVAIL_THRESHOLD_REG_ADDR (0x030036F8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_7__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_7__TILES_FREE_THRESHOLD_REG_ADDR (0x030036FC)

//==============================================================================
// Register File: tile_counters_8_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_8__REG_FILE_BASE_ADDR (0x03003700)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_8__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_8__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_8__RESET_REG_ADDR (0x03003704)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_8__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_8__POSTED_REG_ADDR (0x03003708)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_8__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_8__ACKED_REG_ADDR (0x0300370C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_8__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_8__BUFFER_CAPACITY_REG_ADDR (0x03003710)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_8__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_8__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003718)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_8__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_8__TILES_FREE_THRESHOLD_REG_ADDR (0x0300371C)

//==============================================================================
// Register File: tile_counters_9_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_9__REG_FILE_BASE_ADDR (0x03003720)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_9__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_9__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_9__RESET_REG_ADDR (0x03003724)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_9__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_9__POSTED_REG_ADDR (0x03003728)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_9__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_9__ACKED_REG_ADDR (0x0300372C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_9__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_9__BUFFER_CAPACITY_REG_ADDR (0x03003730)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_9__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_9__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003738)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_9__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_9__TILES_FREE_THRESHOLD_REG_ADDR (0x0300373C)

//==============================================================================
// Register File: tile_counters_10_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_10__REG_FILE_BASE_ADDR (0x03003740)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_10__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_10__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_10__RESET_REG_ADDR (0x03003744)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_10__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_10__POSTED_REG_ADDR (0x03003748)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_10__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_10__ACKED_REG_ADDR (0x0300374C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_10__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_10__BUFFER_CAPACITY_REG_ADDR (0x03003750)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_10__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_10__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003758)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_10__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_10__TILES_FREE_THRESHOLD_REG_ADDR (0x0300375C)

//==============================================================================
// Register File: tile_counters_11_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_11__REG_FILE_BASE_ADDR (0x03003760)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_11__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_11__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_11__RESET_REG_ADDR (0x03003764)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_11__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_11__POSTED_REG_ADDR (0x03003768)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_11__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_11__ACKED_REG_ADDR (0x0300376C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_11__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_11__BUFFER_CAPACITY_REG_ADDR (0x03003770)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_11__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_11__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003778)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_11__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_11__TILES_FREE_THRESHOLD_REG_ADDR (0x0300377C)

//==============================================================================
// Register File: tile_counters_12_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_12__REG_FILE_BASE_ADDR (0x03003780)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_12__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_12__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_12__RESET_REG_ADDR (0x03003784)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_12__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_12__POSTED_REG_ADDR (0x03003788)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_12__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_12__ACKED_REG_ADDR (0x0300378C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_12__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_12__BUFFER_CAPACITY_REG_ADDR (0x03003790)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_12__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_12__TILES_AVAIL_THRESHOLD_REG_ADDR (0x03003798)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_12__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_12__TILES_FREE_THRESHOLD_REG_ADDR (0x0300379C)

//==============================================================================
// Register File: tile_counters_13_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_13__REG_FILE_BASE_ADDR (0x030037A0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_13__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_13__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_13__RESET_REG_ADDR (0x030037A4)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_13__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_13__POSTED_REG_ADDR (0x030037A8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_13__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_13__ACKED_REG_ADDR (0x030037AC)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_13__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_13__BUFFER_CAPACITY_REG_ADDR (0x030037B0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_13__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_13__TILES_AVAIL_THRESHOLD_REG_ADDR (0x030037B8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_13__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_13__TILES_FREE_THRESHOLD_REG_ADDR (0x030037BC)

//==============================================================================
// Register File: tile_counters_14_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_14__REG_FILE_BASE_ADDR (0x030037C0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_14__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_14__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_14__RESET_REG_ADDR (0x030037C4)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_14__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_14__POSTED_REG_ADDR (0x030037C8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_14__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_14__ACKED_REG_ADDR (0x030037CC)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_14__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_14__BUFFER_CAPACITY_REG_ADDR (0x030037D0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_14__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_14__TILES_AVAIL_THRESHOLD_REG_ADDR (0x030037D8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_14__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_14__TILES_FREE_THRESHOLD_REG_ADDR (0x030037DC)

//==============================================================================
// Register File: tile_counters_15_
//==============================================================================

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_15__REG_FILE_BASE_ADDR (0x030037E0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_15__REG_FILE_SIZE (0x00000020)

#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_15__RESET_REG_OFFSET (0x00000004)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_15__RESET_REG_ADDR (0x030037E4)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_15__POSTED_REG_OFFSET (0x00000008)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_15__POSTED_REG_ADDR (0x030037E8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_15__ACKED_REG_OFFSET (0x0000000C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_15__ACKED_REG_ADDR (0x030037EC)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_15__BUFFER_CAPACITY_REG_OFFSET (0x00000010)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_15__BUFFER_CAPACITY_REG_ADDR (0x030037F0)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_15__TILES_AVAIL_THRESHOLD_REG_OFFSET (0x00000018)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_15__TILES_AVAIL_THRESHOLD_REG_ADDR (0x030037F8)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_15__TILES_FREE_THRESHOLD_REG_OFFSET (0x0000001C)
#define TT_OVERLAY_LLK_TILE_COUNTERS_TT_LLK_INTERFACE_3_TILE_COUNTERS_15__TILES_FREE_THRESHOLD_REG_ADDR (0x030037FC)

//==============================================================================
// Addresses for Address Map: tt_rocc_accel
//==============================================================================

#define TT_ROCC_ACCEL_REG_MAP_BASE_ADDR (0x03004000)
#define TT_ROCC_ACCEL_REG_MAP_SIZE (0x00005D48)

//==============================================================================
// Register File: tt_rocc_cpu0_cmd_buf_r
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_REG_FILE_BASE_ADDR (0x03004000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_REG_FILE_SIZE (0x00000148)

#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_IE_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_IE_REG_ADDR (0x03004000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_IP_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_IP_REG_ADDR (0x03004008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_WR_SENT_TR_ID_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_WR_SENT_TR_ID_REG_ADDR (0x03004010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_TR_ACK_TR_ID_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_TR_ACK_TR_ID_REG_ADDR (0x03004018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_SRC_ADDR_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_SRC_ADDR_REG_ADDR (0x03004020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_SRC_BASE_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_SRC_BASE_REG_ADDR (0x03004028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_SRC_SIZE_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_SRC_SIZE_REG_ADDR (0x03004030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_SRC_COORD_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_SRC_COORD_REG_ADDR (0x03004038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_DEST_ADDR_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_DEST_ADDR_REG_ADDR (0x03004040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_DEST_BASE_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_DEST_BASE_REG_ADDR (0x03004048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_DEST_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_DEST_SIZE_REG_ADDR (0x03004050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_DEST_COORD_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_DEST_COORD_REG_ADDR (0x03004058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_LEN_BYTES_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_LEN_BYTES_REG_ADDR (0x03004060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_REQ_VC_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_REQ_VC_REG_ADDR (0x03004068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_REQ_VC_BASE_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_REQ_VC_BASE_REG_ADDR (0x03004070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_REQ_VC_SIZE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_REQ_VC_SIZE_REG_ADDR (0x03004078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_RESP_VC_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_RESP_VC_REG_ADDR (0x03004080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_RESP_VC_BASE_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_RESP_VC_BASE_REG_ADDR (0x03004088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_RESP_VC_SIZE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_RESP_VC_SIZE_REG_ADDR (0x03004090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_TR_ID_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_TR_ID_REG_ADDR (0x03004098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_TR_ID_BASE_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_TR_ID_BASE_REG_ADDR (0x030040A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_TR_ID_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_TR_ID_SIZE_REG_ADDR (0x030040A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_MCAST_EXCLUDE_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_MCAST_EXCLUDE_REG_ADDR (0x030040B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_SCATTER_LIST_ADDR_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_SCATTER_LIST_ADDR_REG_ADDR (0x030040B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_SCATTER_BASE_ADDR_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_SCATTER_BASE_ADDR_REG_ADDR (0x030040C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_SCATTER_INDEX_REG_OFFSET (0x000000C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_SCATTER_INDEX_REG_ADDR (0x030040C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_SCATTER_TIMES_REG_OFFSET (0x000000D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_SCATTER_TIMES_REG_ADDR (0x030040D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_SCATTER_ADDR_0__REG_OFFSET (0x000000D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_SCATTER_ADDR_0__REG_ADDR (0x030040D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_SCATTER_ADDR_1__REG_OFFSET (0x000000E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_SCATTER_ADDR_1__REG_ADDR (0x030040E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_SCATTER_ADDR_2__REG_OFFSET (0x000000E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_SCATTER_ADDR_2__REG_ADDR (0x030040E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_SCATTER_ADDR_3__REG_OFFSET (0x000000F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_SCATTER_ADDR_3__REG_ADDR (0x030040F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_INLINE_DATA_REG_OFFSET (0x000000F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_INLINE_DATA_REG_ADDR (0x030040F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_MAX_BYTES_IN_PACKET_REG_OFFSET (0x00000100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_MAX_BYTES_IN_PACKET_REG_ADDR (0x03004100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_MCAST_DESTS_REG_OFFSET (0x00000108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_MCAST_DESTS_REG_ADDR (0x03004108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_L1_ACCUM_CFG_REG_OFFSET (0x00000110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_L1_ACCUM_CFG_REG_ADDR (0x03004110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_AXI_OPT_1_REG_OFFSET (0x00000118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_AXI_OPT_1_REG_ADDR (0x03004118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_AXI_OPT_2_REG_OFFSET (0x00000120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_AXI_OPT_2_REG_ADDR (0x03004120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_AUTOINC_REG_OFFSET (0x00000128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_AUTOINC_REG_ADDR (0x03004128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_PACKET_TAGS_REG_OFFSET (0x00000130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_PACKET_TAGS_REG_ADDR (0x03004130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_DEBUG_REG_OFFSET (0x00000138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_DEBUG_REG_ADDR (0x03004138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_MISC_REG_OFFSET (0x00000140)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_R_MISC_REG_ADDR (0x03004140)

//==============================================================================
// Register File: tt_rocc_cpu0_cmd_buf_w
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_REG_FILE_BASE_ADDR (0x03004200)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_REG_FILE_SIZE (0x00000148)

#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_IE_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_IE_REG_ADDR (0x03004200)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_IP_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_IP_REG_ADDR (0x03004208)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_WR_SENT_TR_ID_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_WR_SENT_TR_ID_REG_ADDR (0x03004210)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_TR_ACK_TR_ID_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_TR_ACK_TR_ID_REG_ADDR (0x03004218)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_SRC_ADDR_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_SRC_ADDR_REG_ADDR (0x03004220)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_SRC_BASE_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_SRC_BASE_REG_ADDR (0x03004228)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_SRC_SIZE_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_SRC_SIZE_REG_ADDR (0x03004230)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_SRC_COORD_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_SRC_COORD_REG_ADDR (0x03004238)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_DEST_ADDR_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_DEST_ADDR_REG_ADDR (0x03004240)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_DEST_BASE_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_DEST_BASE_REG_ADDR (0x03004248)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_DEST_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_DEST_SIZE_REG_ADDR (0x03004250)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_DEST_COORD_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_DEST_COORD_REG_ADDR (0x03004258)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_LEN_BYTES_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_LEN_BYTES_REG_ADDR (0x03004260)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_REQ_VC_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_REQ_VC_REG_ADDR (0x03004268)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_REQ_VC_BASE_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_REQ_VC_BASE_REG_ADDR (0x03004270)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_REQ_VC_SIZE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_REQ_VC_SIZE_REG_ADDR (0x03004278)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_RESP_VC_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_RESP_VC_REG_ADDR (0x03004280)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_RESP_VC_BASE_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_RESP_VC_BASE_REG_ADDR (0x03004288)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_RESP_VC_SIZE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_RESP_VC_SIZE_REG_ADDR (0x03004290)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_TR_ID_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_TR_ID_REG_ADDR (0x03004298)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_TR_ID_BASE_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_TR_ID_BASE_REG_ADDR (0x030042A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_TR_ID_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_TR_ID_SIZE_REG_ADDR (0x030042A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_MCAST_EXCLUDE_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_MCAST_EXCLUDE_REG_ADDR (0x030042B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_SCATTER_LIST_ADDR_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_SCATTER_LIST_ADDR_REG_ADDR (0x030042B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_SCATTER_BASE_ADDR_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_SCATTER_BASE_ADDR_REG_ADDR (0x030042C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_SCATTER_INDEX_REG_OFFSET (0x000000C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_SCATTER_INDEX_REG_ADDR (0x030042C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_SCATTER_TIMES_REG_OFFSET (0x000000D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_SCATTER_TIMES_REG_ADDR (0x030042D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_SCATTER_ADDR_0__REG_OFFSET (0x000000D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_SCATTER_ADDR_0__REG_ADDR (0x030042D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_SCATTER_ADDR_1__REG_OFFSET (0x000000E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_SCATTER_ADDR_1__REG_ADDR (0x030042E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_SCATTER_ADDR_2__REG_OFFSET (0x000000E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_SCATTER_ADDR_2__REG_ADDR (0x030042E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_SCATTER_ADDR_3__REG_OFFSET (0x000000F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_SCATTER_ADDR_3__REG_ADDR (0x030042F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_INLINE_DATA_REG_OFFSET (0x000000F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_INLINE_DATA_REG_ADDR (0x030042F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_MAX_BYTES_IN_PACKET_REG_OFFSET (0x00000100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_MAX_BYTES_IN_PACKET_REG_ADDR (0x03004300)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_MCAST_DESTS_REG_OFFSET (0x00000108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_MCAST_DESTS_REG_ADDR (0x03004308)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_L1_ACCUM_CFG_REG_OFFSET (0x00000110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_L1_ACCUM_CFG_REG_ADDR (0x03004310)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_AXI_OPT_1_REG_OFFSET (0x00000118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_AXI_OPT_1_REG_ADDR (0x03004318)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_AXI_OPT_2_REG_OFFSET (0x00000120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_AXI_OPT_2_REG_ADDR (0x03004320)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_AUTOINC_REG_OFFSET (0x00000128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_AUTOINC_REG_ADDR (0x03004328)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_PACKET_TAGS_REG_OFFSET (0x00000130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_PACKET_TAGS_REG_ADDR (0x03004330)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_DEBUG_REG_OFFSET (0x00000138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_DEBUG_REG_ADDR (0x03004338)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_MISC_REG_OFFSET (0x00000140)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_CMD_BUF_W_MISC_REG_ADDR (0x03004340)

//==============================================================================
// Register File: tt_rocc_cpu0_address_gen_r
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_REG_FILE_BASE_ADDR (0x03004400)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_REG_FILE_SIZE (0x000000C8)

#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_SRC_BANK_CURRENT_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_SRC_BANK_CURRENT_REG_ADDR (0x03004400)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_SRC_BANK_BASE_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_SRC_BANK_BASE_REG_ADDR (0x03004408)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_SRC_BANK_SIZE_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_SRC_BANK_SIZE_REG_ADDR (0x03004410)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_SRC_BANK_SKIP_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_SRC_BANK_SKIP_REG_ADDR (0x03004418)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_SRC_INNER_STRIDE_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_SRC_INNER_STRIDE_REG_ADDR (0x03004420)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_SRC_INNER_END_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_SRC_INNER_END_REG_ADDR (0x03004428)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_SRC_INNER_ADDRESS_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_SRC_INNER_ADDRESS_REG_ADDR (0x03004430)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_SRC_OUTER_STRIDE_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_SRC_OUTER_STRIDE_REG_ADDR (0x03004438)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_SRC_OUTER_END_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_SRC_OUTER_END_REG_ADDR (0x03004440)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_SRC_OUTER_ADDRESS_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_SRC_OUTER_ADDRESS_REG_ADDR (0x03004448)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_SRC_FACE_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_SRC_FACE_SIZE_REG_ADDR (0x03004450)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_DEST_BANK_CURRENT_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_DEST_BANK_CURRENT_REG_ADDR (0x03004458)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_DEST_BANK_BASE_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_DEST_BANK_BASE_REG_ADDR (0x03004460)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_DEST_BANK_SIZE_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_DEST_BANK_SIZE_REG_ADDR (0x03004468)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_DEST_BANK_SKIP_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_DEST_BANK_SKIP_REG_ADDR (0x03004470)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_DEST_INNER_STRIDE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_DEST_INNER_STRIDE_REG_ADDR (0x03004478)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_DEST_INNER_END_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_DEST_INNER_END_REG_ADDR (0x03004480)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_DEST_INNER_ADDRESS_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_DEST_INNER_ADDRESS_REG_ADDR (0x03004488)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_DEST_OUTER_STRIDE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_DEST_OUTER_STRIDE_REG_ADDR (0x03004490)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_DEST_OUTER_END_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_DEST_OUTER_END_REG_ADDR (0x03004498)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_DEST_OUTER_ADDRESS_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_DEST_OUTER_ADDRESS_REG_ADDR (0x030044A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_DEST_FACE_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_DEST_FACE_SIZE_REG_ADDR (0x030044A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_SRC_GEN_ADDRESS_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_SRC_GEN_ADDRESS_REG_ADDR (0x030044B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_DEST_GEN_ADDRESS_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_DEST_GEN_ADDRESS_REG_ADDR (0x030044B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_MISC_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_R_MISC_REG_ADDR (0x030044C0)

//==============================================================================
// Register File: tt_rocc_cpu0_address_gen_w
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_REG_FILE_BASE_ADDR (0x03004600)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_REG_FILE_SIZE (0x000000C8)

#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_SRC_BANK_CURRENT_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_SRC_BANK_CURRENT_REG_ADDR (0x03004600)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_SRC_BANK_BASE_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_SRC_BANK_BASE_REG_ADDR (0x03004608)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_SRC_BANK_SIZE_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_SRC_BANK_SIZE_REG_ADDR (0x03004610)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_SRC_BANK_SKIP_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_SRC_BANK_SKIP_REG_ADDR (0x03004618)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_SRC_INNER_STRIDE_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_SRC_INNER_STRIDE_REG_ADDR (0x03004620)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_SRC_INNER_END_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_SRC_INNER_END_REG_ADDR (0x03004628)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_SRC_INNER_ADDRESS_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_SRC_INNER_ADDRESS_REG_ADDR (0x03004630)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_SRC_OUTER_STRIDE_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_SRC_OUTER_STRIDE_REG_ADDR (0x03004638)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_SRC_OUTER_END_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_SRC_OUTER_END_REG_ADDR (0x03004640)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_SRC_OUTER_ADDRESS_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_SRC_OUTER_ADDRESS_REG_ADDR (0x03004648)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_SRC_FACE_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_SRC_FACE_SIZE_REG_ADDR (0x03004650)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_DEST_BANK_CURRENT_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_DEST_BANK_CURRENT_REG_ADDR (0x03004658)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_DEST_BANK_BASE_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_DEST_BANK_BASE_REG_ADDR (0x03004660)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_DEST_BANK_SIZE_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_DEST_BANK_SIZE_REG_ADDR (0x03004668)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_DEST_BANK_SKIP_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_DEST_BANK_SKIP_REG_ADDR (0x03004670)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_DEST_INNER_STRIDE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_DEST_INNER_STRIDE_REG_ADDR (0x03004678)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_DEST_INNER_END_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_DEST_INNER_END_REG_ADDR (0x03004680)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_DEST_INNER_ADDRESS_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_DEST_INNER_ADDRESS_REG_ADDR (0x03004688)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_DEST_OUTER_STRIDE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_DEST_OUTER_STRIDE_REG_ADDR (0x03004690)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_DEST_OUTER_END_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_DEST_OUTER_END_REG_ADDR (0x03004698)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_DEST_OUTER_ADDRESS_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_DEST_OUTER_ADDRESS_REG_ADDR (0x030046A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_DEST_FACE_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_DEST_FACE_SIZE_REG_ADDR (0x030046A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_SRC_GEN_ADDRESS_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_SRC_GEN_ADDRESS_REG_ADDR (0x030046B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_DEST_GEN_ADDRESS_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_DEST_GEN_ADDRESS_REG_ADDR (0x030046B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_MISC_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_ADDRESS_GEN_W_MISC_REG_ADDR (0x030046C0)

//==============================================================================
// Register File: tt_rocc_cpu0_simple_cmd_buf
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_REG_FILE_BASE_ADDR (0x03004800)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_REG_FILE_SIZE (0x00000148)

#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_IE_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_IE_REG_ADDR (0x03004800)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_IP_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_IP_REG_ADDR (0x03004808)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_0_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_0_REG_ADDR (0x03004810)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_1_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_1_REG_ADDR (0x03004818)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_SRC_ADDR_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_SRC_ADDR_REG_ADDR (0x03004820)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_2_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_2_REG_ADDR (0x03004828)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_3_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_3_REG_ADDR (0x03004830)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_SRC_COORD_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_SRC_COORD_REG_ADDR (0x03004838)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_DEST_ADDR_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_DEST_ADDR_REG_ADDR (0x03004840)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_4_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_4_REG_ADDR (0x03004848)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_5_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_5_REG_ADDR (0x03004850)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_DEST_COORD_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_DEST_COORD_REG_ADDR (0x03004858)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_LEN_BYTES_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_LEN_BYTES_REG_ADDR (0x03004860)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_REQ_VC_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_REQ_VC_REG_ADDR (0x03004868)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_6_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_6_REG_ADDR (0x03004870)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_7_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_7_REG_ADDR (0x03004878)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESP_VC_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESP_VC_REG_ADDR (0x03004880)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_8_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_8_REG_ADDR (0x03004888)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_9_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_9_REG_ADDR (0x03004890)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_TR_ID_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_TR_ID_REG_ADDR (0x03004898)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_10_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_10_REG_ADDR (0x030048A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_11_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_11_REG_ADDR (0x030048A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_MCAST_EXCLUDE_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_MCAST_EXCLUDE_REG_ADDR (0x030048B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_12_0__REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_12_0__REG_ADDR (0x030048B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_12_1__REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_12_1__REG_ADDR (0x030048C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_12_2__REG_OFFSET (0x000000C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_12_2__REG_ADDR (0x030048C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_12_3__REG_OFFSET (0x000000D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_12_3__REG_ADDR (0x030048D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_12_4__REG_OFFSET (0x000000D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_12_4__REG_ADDR (0x030048D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_12_5__REG_OFFSET (0x000000E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_12_5__REG_ADDR (0x030048E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_12_6__REG_OFFSET (0x000000E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_12_6__REG_ADDR (0x030048E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_12_7__REG_OFFSET (0x000000F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_12_7__REG_ADDR (0x030048F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_INLINE_DATA_REG_OFFSET (0x000000F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_INLINE_DATA_REG_ADDR (0x030048F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_13_REG_OFFSET (0x00000100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_13_REG_ADDR (0x03004900)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_MCAST_DESTS_REG_OFFSET (0x00000108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_MCAST_DESTS_REG_ADDR (0x03004908)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_14_REG_OFFSET (0x00000110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_14_REG_ADDR (0x03004910)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_15_REG_OFFSET (0x00000118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_15_REG_ADDR (0x03004918)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_16_REG_OFFSET (0x00000120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_16_REG_ADDR (0x03004920)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_17_REG_OFFSET (0x00000128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_RESERVED_17_REG_ADDR (0x03004928)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_PACKET_TAGS_REG_OFFSET (0x00000130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_PACKET_TAGS_REG_ADDR (0x03004930)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_DEBUG_REG_OFFSET (0x00000138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_DEBUG_REG_ADDR (0x03004938)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_MISC_REG_OFFSET (0x00000140)
#define TT_ROCC_ACCEL_TT_ROCC_CPU0_SIMPLE_CMD_BUF_MISC_REG_ADDR (0x03004940)

//==============================================================================
// Register File: tt_rocc_cpu1_cmd_buf_r
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_REG_FILE_BASE_ADDR (0x03004C00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_REG_FILE_SIZE (0x00000148)

#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_IE_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_IE_REG_ADDR (0x03004C00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_IP_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_IP_REG_ADDR (0x03004C08)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_WR_SENT_TR_ID_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_WR_SENT_TR_ID_REG_ADDR (0x03004C10)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_TR_ACK_TR_ID_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_TR_ACK_TR_ID_REG_ADDR (0x03004C18)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_SRC_ADDR_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_SRC_ADDR_REG_ADDR (0x03004C20)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_SRC_BASE_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_SRC_BASE_REG_ADDR (0x03004C28)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_SRC_SIZE_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_SRC_SIZE_REG_ADDR (0x03004C30)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_SRC_COORD_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_SRC_COORD_REG_ADDR (0x03004C38)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_DEST_ADDR_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_DEST_ADDR_REG_ADDR (0x03004C40)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_DEST_BASE_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_DEST_BASE_REG_ADDR (0x03004C48)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_DEST_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_DEST_SIZE_REG_ADDR (0x03004C50)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_DEST_COORD_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_DEST_COORD_REG_ADDR (0x03004C58)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_LEN_BYTES_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_LEN_BYTES_REG_ADDR (0x03004C60)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_REQ_VC_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_REQ_VC_REG_ADDR (0x03004C68)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_REQ_VC_BASE_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_REQ_VC_BASE_REG_ADDR (0x03004C70)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_REQ_VC_SIZE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_REQ_VC_SIZE_REG_ADDR (0x03004C78)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_RESP_VC_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_RESP_VC_REG_ADDR (0x03004C80)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_RESP_VC_BASE_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_RESP_VC_BASE_REG_ADDR (0x03004C88)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_RESP_VC_SIZE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_RESP_VC_SIZE_REG_ADDR (0x03004C90)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_TR_ID_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_TR_ID_REG_ADDR (0x03004C98)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_TR_ID_BASE_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_TR_ID_BASE_REG_ADDR (0x03004CA0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_TR_ID_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_TR_ID_SIZE_REG_ADDR (0x03004CA8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_MCAST_EXCLUDE_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_MCAST_EXCLUDE_REG_ADDR (0x03004CB0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_SCATTER_LIST_ADDR_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_SCATTER_LIST_ADDR_REG_ADDR (0x03004CB8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_SCATTER_BASE_ADDR_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_SCATTER_BASE_ADDR_REG_ADDR (0x03004CC0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_SCATTER_INDEX_REG_OFFSET (0x000000C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_SCATTER_INDEX_REG_ADDR (0x03004CC8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_SCATTER_TIMES_REG_OFFSET (0x000000D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_SCATTER_TIMES_REG_ADDR (0x03004CD0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_SCATTER_ADDR_0__REG_OFFSET (0x000000D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_SCATTER_ADDR_0__REG_ADDR (0x03004CD8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_SCATTER_ADDR_1__REG_OFFSET (0x000000E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_SCATTER_ADDR_1__REG_ADDR (0x03004CE0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_SCATTER_ADDR_2__REG_OFFSET (0x000000E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_SCATTER_ADDR_2__REG_ADDR (0x03004CE8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_SCATTER_ADDR_3__REG_OFFSET (0x000000F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_SCATTER_ADDR_3__REG_ADDR (0x03004CF0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_INLINE_DATA_REG_OFFSET (0x000000F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_INLINE_DATA_REG_ADDR (0x03004CF8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_MAX_BYTES_IN_PACKET_REG_OFFSET (0x00000100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_MAX_BYTES_IN_PACKET_REG_ADDR (0x03004D00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_MCAST_DESTS_REG_OFFSET (0x00000108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_MCAST_DESTS_REG_ADDR (0x03004D08)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_L1_ACCUM_CFG_REG_OFFSET (0x00000110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_L1_ACCUM_CFG_REG_ADDR (0x03004D10)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_AXI_OPT_1_REG_OFFSET (0x00000118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_AXI_OPT_1_REG_ADDR (0x03004D18)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_AXI_OPT_2_REG_OFFSET (0x00000120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_AXI_OPT_2_REG_ADDR (0x03004D20)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_AUTOINC_REG_OFFSET (0x00000128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_AUTOINC_REG_ADDR (0x03004D28)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_PACKET_TAGS_REG_OFFSET (0x00000130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_PACKET_TAGS_REG_ADDR (0x03004D30)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_DEBUG_REG_OFFSET (0x00000138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_DEBUG_REG_ADDR (0x03004D38)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_MISC_REG_OFFSET (0x00000140)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_R_MISC_REG_ADDR (0x03004D40)

//==============================================================================
// Register File: tt_rocc_cpu1_cmd_buf_w
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_REG_FILE_BASE_ADDR (0x03004E00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_REG_FILE_SIZE (0x00000148)

#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_IE_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_IE_REG_ADDR (0x03004E00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_IP_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_IP_REG_ADDR (0x03004E08)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_WR_SENT_TR_ID_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_WR_SENT_TR_ID_REG_ADDR (0x03004E10)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_TR_ACK_TR_ID_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_TR_ACK_TR_ID_REG_ADDR (0x03004E18)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_SRC_ADDR_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_SRC_ADDR_REG_ADDR (0x03004E20)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_SRC_BASE_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_SRC_BASE_REG_ADDR (0x03004E28)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_SRC_SIZE_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_SRC_SIZE_REG_ADDR (0x03004E30)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_SRC_COORD_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_SRC_COORD_REG_ADDR (0x03004E38)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_DEST_ADDR_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_DEST_ADDR_REG_ADDR (0x03004E40)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_DEST_BASE_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_DEST_BASE_REG_ADDR (0x03004E48)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_DEST_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_DEST_SIZE_REG_ADDR (0x03004E50)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_DEST_COORD_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_DEST_COORD_REG_ADDR (0x03004E58)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_LEN_BYTES_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_LEN_BYTES_REG_ADDR (0x03004E60)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_REQ_VC_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_REQ_VC_REG_ADDR (0x03004E68)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_REQ_VC_BASE_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_REQ_VC_BASE_REG_ADDR (0x03004E70)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_REQ_VC_SIZE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_REQ_VC_SIZE_REG_ADDR (0x03004E78)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_RESP_VC_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_RESP_VC_REG_ADDR (0x03004E80)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_RESP_VC_BASE_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_RESP_VC_BASE_REG_ADDR (0x03004E88)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_RESP_VC_SIZE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_RESP_VC_SIZE_REG_ADDR (0x03004E90)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_TR_ID_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_TR_ID_REG_ADDR (0x03004E98)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_TR_ID_BASE_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_TR_ID_BASE_REG_ADDR (0x03004EA0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_TR_ID_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_TR_ID_SIZE_REG_ADDR (0x03004EA8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_MCAST_EXCLUDE_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_MCAST_EXCLUDE_REG_ADDR (0x03004EB0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_SCATTER_LIST_ADDR_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_SCATTER_LIST_ADDR_REG_ADDR (0x03004EB8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_SCATTER_BASE_ADDR_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_SCATTER_BASE_ADDR_REG_ADDR (0x03004EC0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_SCATTER_INDEX_REG_OFFSET (0x000000C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_SCATTER_INDEX_REG_ADDR (0x03004EC8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_SCATTER_TIMES_REG_OFFSET (0x000000D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_SCATTER_TIMES_REG_ADDR (0x03004ED0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_SCATTER_ADDR_0__REG_OFFSET (0x000000D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_SCATTER_ADDR_0__REG_ADDR (0x03004ED8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_SCATTER_ADDR_1__REG_OFFSET (0x000000E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_SCATTER_ADDR_1__REG_ADDR (0x03004EE0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_SCATTER_ADDR_2__REG_OFFSET (0x000000E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_SCATTER_ADDR_2__REG_ADDR (0x03004EE8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_SCATTER_ADDR_3__REG_OFFSET (0x000000F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_SCATTER_ADDR_3__REG_ADDR (0x03004EF0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_INLINE_DATA_REG_OFFSET (0x000000F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_INLINE_DATA_REG_ADDR (0x03004EF8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_MAX_BYTES_IN_PACKET_REG_OFFSET (0x00000100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_MAX_BYTES_IN_PACKET_REG_ADDR (0x03004F00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_MCAST_DESTS_REG_OFFSET (0x00000108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_MCAST_DESTS_REG_ADDR (0x03004F08)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_L1_ACCUM_CFG_REG_OFFSET (0x00000110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_L1_ACCUM_CFG_REG_ADDR (0x03004F10)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_AXI_OPT_1_REG_OFFSET (0x00000118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_AXI_OPT_1_REG_ADDR (0x03004F18)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_AXI_OPT_2_REG_OFFSET (0x00000120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_AXI_OPT_2_REG_ADDR (0x03004F20)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_AUTOINC_REG_OFFSET (0x00000128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_AUTOINC_REG_ADDR (0x03004F28)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_PACKET_TAGS_REG_OFFSET (0x00000130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_PACKET_TAGS_REG_ADDR (0x03004F30)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_DEBUG_REG_OFFSET (0x00000138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_DEBUG_REG_ADDR (0x03004F38)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_MISC_REG_OFFSET (0x00000140)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_CMD_BUF_W_MISC_REG_ADDR (0x03004F40)

//==============================================================================
// Register File: tt_rocc_cpu1_address_gen_r
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_REG_FILE_BASE_ADDR (0x03005000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_REG_FILE_SIZE (0x000000C8)

#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_SRC_BANK_CURRENT_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_SRC_BANK_CURRENT_REG_ADDR (0x03005000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_SRC_BANK_BASE_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_SRC_BANK_BASE_REG_ADDR (0x03005008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_SRC_BANK_SIZE_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_SRC_BANK_SIZE_REG_ADDR (0x03005010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_SRC_BANK_SKIP_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_SRC_BANK_SKIP_REG_ADDR (0x03005018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_SRC_INNER_STRIDE_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_SRC_INNER_STRIDE_REG_ADDR (0x03005020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_SRC_INNER_END_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_SRC_INNER_END_REG_ADDR (0x03005028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_SRC_INNER_ADDRESS_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_SRC_INNER_ADDRESS_REG_ADDR (0x03005030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_SRC_OUTER_STRIDE_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_SRC_OUTER_STRIDE_REG_ADDR (0x03005038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_SRC_OUTER_END_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_SRC_OUTER_END_REG_ADDR (0x03005040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_SRC_OUTER_ADDRESS_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_SRC_OUTER_ADDRESS_REG_ADDR (0x03005048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_SRC_FACE_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_SRC_FACE_SIZE_REG_ADDR (0x03005050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_DEST_BANK_CURRENT_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_DEST_BANK_CURRENT_REG_ADDR (0x03005058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_DEST_BANK_BASE_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_DEST_BANK_BASE_REG_ADDR (0x03005060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_DEST_BANK_SIZE_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_DEST_BANK_SIZE_REG_ADDR (0x03005068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_DEST_BANK_SKIP_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_DEST_BANK_SKIP_REG_ADDR (0x03005070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_DEST_INNER_STRIDE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_DEST_INNER_STRIDE_REG_ADDR (0x03005078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_DEST_INNER_END_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_DEST_INNER_END_REG_ADDR (0x03005080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_DEST_INNER_ADDRESS_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_DEST_INNER_ADDRESS_REG_ADDR (0x03005088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_DEST_OUTER_STRIDE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_DEST_OUTER_STRIDE_REG_ADDR (0x03005090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_DEST_OUTER_END_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_DEST_OUTER_END_REG_ADDR (0x03005098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_DEST_OUTER_ADDRESS_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_DEST_OUTER_ADDRESS_REG_ADDR (0x030050A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_DEST_FACE_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_DEST_FACE_SIZE_REG_ADDR (0x030050A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_SRC_GEN_ADDRESS_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_SRC_GEN_ADDRESS_REG_ADDR (0x030050B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_DEST_GEN_ADDRESS_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_DEST_GEN_ADDRESS_REG_ADDR (0x030050B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_MISC_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_R_MISC_REG_ADDR (0x030050C0)

//==============================================================================
// Register File: tt_rocc_cpu1_address_gen_w
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_REG_FILE_BASE_ADDR (0x03005200)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_REG_FILE_SIZE (0x000000C8)

#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_SRC_BANK_CURRENT_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_SRC_BANK_CURRENT_REG_ADDR (0x03005200)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_SRC_BANK_BASE_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_SRC_BANK_BASE_REG_ADDR (0x03005208)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_SRC_BANK_SIZE_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_SRC_BANK_SIZE_REG_ADDR (0x03005210)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_SRC_BANK_SKIP_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_SRC_BANK_SKIP_REG_ADDR (0x03005218)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_SRC_INNER_STRIDE_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_SRC_INNER_STRIDE_REG_ADDR (0x03005220)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_SRC_INNER_END_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_SRC_INNER_END_REG_ADDR (0x03005228)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_SRC_INNER_ADDRESS_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_SRC_INNER_ADDRESS_REG_ADDR (0x03005230)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_SRC_OUTER_STRIDE_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_SRC_OUTER_STRIDE_REG_ADDR (0x03005238)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_SRC_OUTER_END_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_SRC_OUTER_END_REG_ADDR (0x03005240)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_SRC_OUTER_ADDRESS_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_SRC_OUTER_ADDRESS_REG_ADDR (0x03005248)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_SRC_FACE_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_SRC_FACE_SIZE_REG_ADDR (0x03005250)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_DEST_BANK_CURRENT_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_DEST_BANK_CURRENT_REG_ADDR (0x03005258)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_DEST_BANK_BASE_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_DEST_BANK_BASE_REG_ADDR (0x03005260)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_DEST_BANK_SIZE_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_DEST_BANK_SIZE_REG_ADDR (0x03005268)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_DEST_BANK_SKIP_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_DEST_BANK_SKIP_REG_ADDR (0x03005270)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_DEST_INNER_STRIDE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_DEST_INNER_STRIDE_REG_ADDR (0x03005278)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_DEST_INNER_END_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_DEST_INNER_END_REG_ADDR (0x03005280)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_DEST_INNER_ADDRESS_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_DEST_INNER_ADDRESS_REG_ADDR (0x03005288)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_DEST_OUTER_STRIDE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_DEST_OUTER_STRIDE_REG_ADDR (0x03005290)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_DEST_OUTER_END_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_DEST_OUTER_END_REG_ADDR (0x03005298)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_DEST_OUTER_ADDRESS_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_DEST_OUTER_ADDRESS_REG_ADDR (0x030052A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_DEST_FACE_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_DEST_FACE_SIZE_REG_ADDR (0x030052A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_SRC_GEN_ADDRESS_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_SRC_GEN_ADDRESS_REG_ADDR (0x030052B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_DEST_GEN_ADDRESS_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_DEST_GEN_ADDRESS_REG_ADDR (0x030052B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_MISC_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_ADDRESS_GEN_W_MISC_REG_ADDR (0x030052C0)

//==============================================================================
// Register File: tt_rocc_cpu1_simple_cmd_buf
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_REG_FILE_BASE_ADDR (0x03005400)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_REG_FILE_SIZE (0x00000148)

#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_IE_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_IE_REG_ADDR (0x03005400)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_IP_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_IP_REG_ADDR (0x03005408)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_0_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_0_REG_ADDR (0x03005410)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_1_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_1_REG_ADDR (0x03005418)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_SRC_ADDR_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_SRC_ADDR_REG_ADDR (0x03005420)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_2_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_2_REG_ADDR (0x03005428)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_3_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_3_REG_ADDR (0x03005430)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_SRC_COORD_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_SRC_COORD_REG_ADDR (0x03005438)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_DEST_ADDR_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_DEST_ADDR_REG_ADDR (0x03005440)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_4_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_4_REG_ADDR (0x03005448)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_5_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_5_REG_ADDR (0x03005450)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_DEST_COORD_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_DEST_COORD_REG_ADDR (0x03005458)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_LEN_BYTES_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_LEN_BYTES_REG_ADDR (0x03005460)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_REQ_VC_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_REQ_VC_REG_ADDR (0x03005468)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_6_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_6_REG_ADDR (0x03005470)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_7_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_7_REG_ADDR (0x03005478)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESP_VC_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESP_VC_REG_ADDR (0x03005480)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_8_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_8_REG_ADDR (0x03005488)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_9_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_9_REG_ADDR (0x03005490)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_TR_ID_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_TR_ID_REG_ADDR (0x03005498)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_10_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_10_REG_ADDR (0x030054A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_11_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_11_REG_ADDR (0x030054A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_MCAST_EXCLUDE_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_MCAST_EXCLUDE_REG_ADDR (0x030054B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_12_0__REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_12_0__REG_ADDR (0x030054B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_12_1__REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_12_1__REG_ADDR (0x030054C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_12_2__REG_OFFSET (0x000000C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_12_2__REG_ADDR (0x030054C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_12_3__REG_OFFSET (0x000000D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_12_3__REG_ADDR (0x030054D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_12_4__REG_OFFSET (0x000000D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_12_4__REG_ADDR (0x030054D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_12_5__REG_OFFSET (0x000000E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_12_5__REG_ADDR (0x030054E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_12_6__REG_OFFSET (0x000000E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_12_6__REG_ADDR (0x030054E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_12_7__REG_OFFSET (0x000000F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_12_7__REG_ADDR (0x030054F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_INLINE_DATA_REG_OFFSET (0x000000F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_INLINE_DATA_REG_ADDR (0x030054F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_13_REG_OFFSET (0x00000100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_13_REG_ADDR (0x03005500)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_MCAST_DESTS_REG_OFFSET (0x00000108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_MCAST_DESTS_REG_ADDR (0x03005508)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_14_REG_OFFSET (0x00000110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_14_REG_ADDR (0x03005510)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_15_REG_OFFSET (0x00000118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_15_REG_ADDR (0x03005518)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_16_REG_OFFSET (0x00000120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_16_REG_ADDR (0x03005520)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_17_REG_OFFSET (0x00000128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_RESERVED_17_REG_ADDR (0x03005528)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_PACKET_TAGS_REG_OFFSET (0x00000130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_PACKET_TAGS_REG_ADDR (0x03005530)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_DEBUG_REG_OFFSET (0x00000138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_DEBUG_REG_ADDR (0x03005538)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_MISC_REG_OFFSET (0x00000140)
#define TT_ROCC_ACCEL_TT_ROCC_CPU1_SIMPLE_CMD_BUF_MISC_REG_ADDR (0x03005540)

//==============================================================================
// Register File: tt_rocc_cpu2_cmd_buf_r
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_REG_FILE_BASE_ADDR (0x03005800)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_REG_FILE_SIZE (0x00000148)

#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_IE_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_IE_REG_ADDR (0x03005800)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_IP_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_IP_REG_ADDR (0x03005808)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_WR_SENT_TR_ID_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_WR_SENT_TR_ID_REG_ADDR (0x03005810)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_TR_ACK_TR_ID_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_TR_ACK_TR_ID_REG_ADDR (0x03005818)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_SRC_ADDR_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_SRC_ADDR_REG_ADDR (0x03005820)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_SRC_BASE_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_SRC_BASE_REG_ADDR (0x03005828)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_SRC_SIZE_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_SRC_SIZE_REG_ADDR (0x03005830)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_SRC_COORD_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_SRC_COORD_REG_ADDR (0x03005838)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_DEST_ADDR_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_DEST_ADDR_REG_ADDR (0x03005840)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_DEST_BASE_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_DEST_BASE_REG_ADDR (0x03005848)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_DEST_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_DEST_SIZE_REG_ADDR (0x03005850)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_DEST_COORD_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_DEST_COORD_REG_ADDR (0x03005858)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_LEN_BYTES_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_LEN_BYTES_REG_ADDR (0x03005860)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_REQ_VC_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_REQ_VC_REG_ADDR (0x03005868)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_REQ_VC_BASE_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_REQ_VC_BASE_REG_ADDR (0x03005870)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_REQ_VC_SIZE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_REQ_VC_SIZE_REG_ADDR (0x03005878)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_RESP_VC_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_RESP_VC_REG_ADDR (0x03005880)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_RESP_VC_BASE_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_RESP_VC_BASE_REG_ADDR (0x03005888)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_RESP_VC_SIZE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_RESP_VC_SIZE_REG_ADDR (0x03005890)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_TR_ID_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_TR_ID_REG_ADDR (0x03005898)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_TR_ID_BASE_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_TR_ID_BASE_REG_ADDR (0x030058A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_TR_ID_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_TR_ID_SIZE_REG_ADDR (0x030058A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_MCAST_EXCLUDE_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_MCAST_EXCLUDE_REG_ADDR (0x030058B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_SCATTER_LIST_ADDR_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_SCATTER_LIST_ADDR_REG_ADDR (0x030058B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_SCATTER_BASE_ADDR_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_SCATTER_BASE_ADDR_REG_ADDR (0x030058C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_SCATTER_INDEX_REG_OFFSET (0x000000C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_SCATTER_INDEX_REG_ADDR (0x030058C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_SCATTER_TIMES_REG_OFFSET (0x000000D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_SCATTER_TIMES_REG_ADDR (0x030058D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_SCATTER_ADDR_0__REG_OFFSET (0x000000D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_SCATTER_ADDR_0__REG_ADDR (0x030058D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_SCATTER_ADDR_1__REG_OFFSET (0x000000E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_SCATTER_ADDR_1__REG_ADDR (0x030058E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_SCATTER_ADDR_2__REG_OFFSET (0x000000E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_SCATTER_ADDR_2__REG_ADDR (0x030058E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_SCATTER_ADDR_3__REG_OFFSET (0x000000F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_SCATTER_ADDR_3__REG_ADDR (0x030058F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_INLINE_DATA_REG_OFFSET (0x000000F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_INLINE_DATA_REG_ADDR (0x030058F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_MAX_BYTES_IN_PACKET_REG_OFFSET (0x00000100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_MAX_BYTES_IN_PACKET_REG_ADDR (0x03005900)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_MCAST_DESTS_REG_OFFSET (0x00000108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_MCAST_DESTS_REG_ADDR (0x03005908)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_L1_ACCUM_CFG_REG_OFFSET (0x00000110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_L1_ACCUM_CFG_REG_ADDR (0x03005910)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_AXI_OPT_1_REG_OFFSET (0x00000118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_AXI_OPT_1_REG_ADDR (0x03005918)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_AXI_OPT_2_REG_OFFSET (0x00000120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_AXI_OPT_2_REG_ADDR (0x03005920)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_AUTOINC_REG_OFFSET (0x00000128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_AUTOINC_REG_ADDR (0x03005928)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_PACKET_TAGS_REG_OFFSET (0x00000130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_PACKET_TAGS_REG_ADDR (0x03005930)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_DEBUG_REG_OFFSET (0x00000138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_DEBUG_REG_ADDR (0x03005938)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_MISC_REG_OFFSET (0x00000140)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_R_MISC_REG_ADDR (0x03005940)

//==============================================================================
// Register File: tt_rocc_cpu2_cmd_buf_w
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_REG_FILE_BASE_ADDR (0x03005A00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_REG_FILE_SIZE (0x00000148)

#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_IE_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_IE_REG_ADDR (0x03005A00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_IP_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_IP_REG_ADDR (0x03005A08)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_WR_SENT_TR_ID_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_WR_SENT_TR_ID_REG_ADDR (0x03005A10)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_TR_ACK_TR_ID_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_TR_ACK_TR_ID_REG_ADDR (0x03005A18)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_SRC_ADDR_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_SRC_ADDR_REG_ADDR (0x03005A20)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_SRC_BASE_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_SRC_BASE_REG_ADDR (0x03005A28)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_SRC_SIZE_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_SRC_SIZE_REG_ADDR (0x03005A30)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_SRC_COORD_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_SRC_COORD_REG_ADDR (0x03005A38)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_DEST_ADDR_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_DEST_ADDR_REG_ADDR (0x03005A40)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_DEST_BASE_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_DEST_BASE_REG_ADDR (0x03005A48)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_DEST_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_DEST_SIZE_REG_ADDR (0x03005A50)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_DEST_COORD_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_DEST_COORD_REG_ADDR (0x03005A58)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_LEN_BYTES_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_LEN_BYTES_REG_ADDR (0x03005A60)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_REQ_VC_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_REQ_VC_REG_ADDR (0x03005A68)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_REQ_VC_BASE_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_REQ_VC_BASE_REG_ADDR (0x03005A70)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_REQ_VC_SIZE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_REQ_VC_SIZE_REG_ADDR (0x03005A78)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_RESP_VC_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_RESP_VC_REG_ADDR (0x03005A80)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_RESP_VC_BASE_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_RESP_VC_BASE_REG_ADDR (0x03005A88)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_RESP_VC_SIZE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_RESP_VC_SIZE_REG_ADDR (0x03005A90)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_TR_ID_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_TR_ID_REG_ADDR (0x03005A98)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_TR_ID_BASE_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_TR_ID_BASE_REG_ADDR (0x03005AA0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_TR_ID_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_TR_ID_SIZE_REG_ADDR (0x03005AA8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_MCAST_EXCLUDE_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_MCAST_EXCLUDE_REG_ADDR (0x03005AB0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_SCATTER_LIST_ADDR_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_SCATTER_LIST_ADDR_REG_ADDR (0x03005AB8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_SCATTER_BASE_ADDR_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_SCATTER_BASE_ADDR_REG_ADDR (0x03005AC0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_SCATTER_INDEX_REG_OFFSET (0x000000C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_SCATTER_INDEX_REG_ADDR (0x03005AC8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_SCATTER_TIMES_REG_OFFSET (0x000000D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_SCATTER_TIMES_REG_ADDR (0x03005AD0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_SCATTER_ADDR_0__REG_OFFSET (0x000000D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_SCATTER_ADDR_0__REG_ADDR (0x03005AD8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_SCATTER_ADDR_1__REG_OFFSET (0x000000E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_SCATTER_ADDR_1__REG_ADDR (0x03005AE0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_SCATTER_ADDR_2__REG_OFFSET (0x000000E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_SCATTER_ADDR_2__REG_ADDR (0x03005AE8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_SCATTER_ADDR_3__REG_OFFSET (0x000000F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_SCATTER_ADDR_3__REG_ADDR (0x03005AF0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_INLINE_DATA_REG_OFFSET (0x000000F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_INLINE_DATA_REG_ADDR (0x03005AF8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_MAX_BYTES_IN_PACKET_REG_OFFSET (0x00000100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_MAX_BYTES_IN_PACKET_REG_ADDR (0x03005B00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_MCAST_DESTS_REG_OFFSET (0x00000108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_MCAST_DESTS_REG_ADDR (0x03005B08)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_L1_ACCUM_CFG_REG_OFFSET (0x00000110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_L1_ACCUM_CFG_REG_ADDR (0x03005B10)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_AXI_OPT_1_REG_OFFSET (0x00000118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_AXI_OPT_1_REG_ADDR (0x03005B18)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_AXI_OPT_2_REG_OFFSET (0x00000120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_AXI_OPT_2_REG_ADDR (0x03005B20)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_AUTOINC_REG_OFFSET (0x00000128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_AUTOINC_REG_ADDR (0x03005B28)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_PACKET_TAGS_REG_OFFSET (0x00000130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_PACKET_TAGS_REG_ADDR (0x03005B30)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_DEBUG_REG_OFFSET (0x00000138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_DEBUG_REG_ADDR (0x03005B38)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_MISC_REG_OFFSET (0x00000140)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_CMD_BUF_W_MISC_REG_ADDR (0x03005B40)

//==============================================================================
// Register File: tt_rocc_cpu2_address_gen_r
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_REG_FILE_BASE_ADDR (0x03005C00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_REG_FILE_SIZE (0x000000C8)

#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_SRC_BANK_CURRENT_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_SRC_BANK_CURRENT_REG_ADDR (0x03005C00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_SRC_BANK_BASE_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_SRC_BANK_BASE_REG_ADDR (0x03005C08)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_SRC_BANK_SIZE_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_SRC_BANK_SIZE_REG_ADDR (0x03005C10)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_SRC_BANK_SKIP_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_SRC_BANK_SKIP_REG_ADDR (0x03005C18)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_SRC_INNER_STRIDE_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_SRC_INNER_STRIDE_REG_ADDR (0x03005C20)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_SRC_INNER_END_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_SRC_INNER_END_REG_ADDR (0x03005C28)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_SRC_INNER_ADDRESS_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_SRC_INNER_ADDRESS_REG_ADDR (0x03005C30)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_SRC_OUTER_STRIDE_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_SRC_OUTER_STRIDE_REG_ADDR (0x03005C38)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_SRC_OUTER_END_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_SRC_OUTER_END_REG_ADDR (0x03005C40)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_SRC_OUTER_ADDRESS_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_SRC_OUTER_ADDRESS_REG_ADDR (0x03005C48)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_SRC_FACE_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_SRC_FACE_SIZE_REG_ADDR (0x03005C50)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_DEST_BANK_CURRENT_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_DEST_BANK_CURRENT_REG_ADDR (0x03005C58)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_DEST_BANK_BASE_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_DEST_BANK_BASE_REG_ADDR (0x03005C60)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_DEST_BANK_SIZE_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_DEST_BANK_SIZE_REG_ADDR (0x03005C68)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_DEST_BANK_SKIP_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_DEST_BANK_SKIP_REG_ADDR (0x03005C70)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_DEST_INNER_STRIDE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_DEST_INNER_STRIDE_REG_ADDR (0x03005C78)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_DEST_INNER_END_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_DEST_INNER_END_REG_ADDR (0x03005C80)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_DEST_INNER_ADDRESS_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_DEST_INNER_ADDRESS_REG_ADDR (0x03005C88)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_DEST_OUTER_STRIDE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_DEST_OUTER_STRIDE_REG_ADDR (0x03005C90)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_DEST_OUTER_END_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_DEST_OUTER_END_REG_ADDR (0x03005C98)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_DEST_OUTER_ADDRESS_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_DEST_OUTER_ADDRESS_REG_ADDR (0x03005CA0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_DEST_FACE_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_DEST_FACE_SIZE_REG_ADDR (0x03005CA8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_SRC_GEN_ADDRESS_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_SRC_GEN_ADDRESS_REG_ADDR (0x03005CB0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_DEST_GEN_ADDRESS_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_DEST_GEN_ADDRESS_REG_ADDR (0x03005CB8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_MISC_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_R_MISC_REG_ADDR (0x03005CC0)

//==============================================================================
// Register File: tt_rocc_cpu2_address_gen_w
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_REG_FILE_BASE_ADDR (0x03005E00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_REG_FILE_SIZE (0x000000C8)

#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_SRC_BANK_CURRENT_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_SRC_BANK_CURRENT_REG_ADDR (0x03005E00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_SRC_BANK_BASE_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_SRC_BANK_BASE_REG_ADDR (0x03005E08)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_SRC_BANK_SIZE_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_SRC_BANK_SIZE_REG_ADDR (0x03005E10)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_SRC_BANK_SKIP_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_SRC_BANK_SKIP_REG_ADDR (0x03005E18)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_SRC_INNER_STRIDE_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_SRC_INNER_STRIDE_REG_ADDR (0x03005E20)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_SRC_INNER_END_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_SRC_INNER_END_REG_ADDR (0x03005E28)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_SRC_INNER_ADDRESS_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_SRC_INNER_ADDRESS_REG_ADDR (0x03005E30)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_SRC_OUTER_STRIDE_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_SRC_OUTER_STRIDE_REG_ADDR (0x03005E38)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_SRC_OUTER_END_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_SRC_OUTER_END_REG_ADDR (0x03005E40)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_SRC_OUTER_ADDRESS_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_SRC_OUTER_ADDRESS_REG_ADDR (0x03005E48)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_SRC_FACE_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_SRC_FACE_SIZE_REG_ADDR (0x03005E50)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_DEST_BANK_CURRENT_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_DEST_BANK_CURRENT_REG_ADDR (0x03005E58)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_DEST_BANK_BASE_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_DEST_BANK_BASE_REG_ADDR (0x03005E60)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_DEST_BANK_SIZE_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_DEST_BANK_SIZE_REG_ADDR (0x03005E68)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_DEST_BANK_SKIP_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_DEST_BANK_SKIP_REG_ADDR (0x03005E70)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_DEST_INNER_STRIDE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_DEST_INNER_STRIDE_REG_ADDR (0x03005E78)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_DEST_INNER_END_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_DEST_INNER_END_REG_ADDR (0x03005E80)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_DEST_INNER_ADDRESS_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_DEST_INNER_ADDRESS_REG_ADDR (0x03005E88)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_DEST_OUTER_STRIDE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_DEST_OUTER_STRIDE_REG_ADDR (0x03005E90)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_DEST_OUTER_END_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_DEST_OUTER_END_REG_ADDR (0x03005E98)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_DEST_OUTER_ADDRESS_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_DEST_OUTER_ADDRESS_REG_ADDR (0x03005EA0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_DEST_FACE_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_DEST_FACE_SIZE_REG_ADDR (0x03005EA8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_SRC_GEN_ADDRESS_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_SRC_GEN_ADDRESS_REG_ADDR (0x03005EB0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_DEST_GEN_ADDRESS_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_DEST_GEN_ADDRESS_REG_ADDR (0x03005EB8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_MISC_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_ADDRESS_GEN_W_MISC_REG_ADDR (0x03005EC0)

//==============================================================================
// Register File: tt_rocc_cpu2_simple_cmd_buf
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_REG_FILE_BASE_ADDR (0x03006000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_REG_FILE_SIZE (0x00000148)

#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_IE_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_IE_REG_ADDR (0x03006000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_IP_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_IP_REG_ADDR (0x03006008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_0_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_0_REG_ADDR (0x03006010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_1_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_1_REG_ADDR (0x03006018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_SRC_ADDR_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_SRC_ADDR_REG_ADDR (0x03006020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_2_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_2_REG_ADDR (0x03006028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_3_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_3_REG_ADDR (0x03006030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_SRC_COORD_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_SRC_COORD_REG_ADDR (0x03006038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_DEST_ADDR_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_DEST_ADDR_REG_ADDR (0x03006040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_4_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_4_REG_ADDR (0x03006048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_5_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_5_REG_ADDR (0x03006050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_DEST_COORD_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_DEST_COORD_REG_ADDR (0x03006058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_LEN_BYTES_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_LEN_BYTES_REG_ADDR (0x03006060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_REQ_VC_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_REQ_VC_REG_ADDR (0x03006068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_6_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_6_REG_ADDR (0x03006070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_7_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_7_REG_ADDR (0x03006078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESP_VC_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESP_VC_REG_ADDR (0x03006080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_8_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_8_REG_ADDR (0x03006088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_9_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_9_REG_ADDR (0x03006090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_TR_ID_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_TR_ID_REG_ADDR (0x03006098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_10_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_10_REG_ADDR (0x030060A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_11_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_11_REG_ADDR (0x030060A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_MCAST_EXCLUDE_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_MCAST_EXCLUDE_REG_ADDR (0x030060B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_12_0__REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_12_0__REG_ADDR (0x030060B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_12_1__REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_12_1__REG_ADDR (0x030060C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_12_2__REG_OFFSET (0x000000C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_12_2__REG_ADDR (0x030060C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_12_3__REG_OFFSET (0x000000D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_12_3__REG_ADDR (0x030060D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_12_4__REG_OFFSET (0x000000D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_12_4__REG_ADDR (0x030060D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_12_5__REG_OFFSET (0x000000E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_12_5__REG_ADDR (0x030060E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_12_6__REG_OFFSET (0x000000E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_12_6__REG_ADDR (0x030060E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_12_7__REG_OFFSET (0x000000F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_12_7__REG_ADDR (0x030060F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_INLINE_DATA_REG_OFFSET (0x000000F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_INLINE_DATA_REG_ADDR (0x030060F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_13_REG_OFFSET (0x00000100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_13_REG_ADDR (0x03006100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_MCAST_DESTS_REG_OFFSET (0x00000108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_MCAST_DESTS_REG_ADDR (0x03006108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_14_REG_OFFSET (0x00000110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_14_REG_ADDR (0x03006110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_15_REG_OFFSET (0x00000118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_15_REG_ADDR (0x03006118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_16_REG_OFFSET (0x00000120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_16_REG_ADDR (0x03006120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_17_REG_OFFSET (0x00000128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_RESERVED_17_REG_ADDR (0x03006128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_PACKET_TAGS_REG_OFFSET (0x00000130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_PACKET_TAGS_REG_ADDR (0x03006130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_DEBUG_REG_OFFSET (0x00000138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_DEBUG_REG_ADDR (0x03006138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_MISC_REG_OFFSET (0x00000140)
#define TT_ROCC_ACCEL_TT_ROCC_CPU2_SIMPLE_CMD_BUF_MISC_REG_ADDR (0x03006140)

//==============================================================================
// Register File: tt_rocc_cpu3_cmd_buf_r
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_REG_FILE_BASE_ADDR (0x03006400)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_REG_FILE_SIZE (0x00000148)

#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_IE_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_IE_REG_ADDR (0x03006400)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_IP_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_IP_REG_ADDR (0x03006408)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_WR_SENT_TR_ID_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_WR_SENT_TR_ID_REG_ADDR (0x03006410)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_TR_ACK_TR_ID_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_TR_ACK_TR_ID_REG_ADDR (0x03006418)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_SRC_ADDR_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_SRC_ADDR_REG_ADDR (0x03006420)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_SRC_BASE_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_SRC_BASE_REG_ADDR (0x03006428)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_SRC_SIZE_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_SRC_SIZE_REG_ADDR (0x03006430)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_SRC_COORD_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_SRC_COORD_REG_ADDR (0x03006438)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_DEST_ADDR_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_DEST_ADDR_REG_ADDR (0x03006440)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_DEST_BASE_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_DEST_BASE_REG_ADDR (0x03006448)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_DEST_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_DEST_SIZE_REG_ADDR (0x03006450)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_DEST_COORD_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_DEST_COORD_REG_ADDR (0x03006458)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_LEN_BYTES_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_LEN_BYTES_REG_ADDR (0x03006460)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_REQ_VC_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_REQ_VC_REG_ADDR (0x03006468)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_REQ_VC_BASE_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_REQ_VC_BASE_REG_ADDR (0x03006470)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_REQ_VC_SIZE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_REQ_VC_SIZE_REG_ADDR (0x03006478)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_RESP_VC_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_RESP_VC_REG_ADDR (0x03006480)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_RESP_VC_BASE_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_RESP_VC_BASE_REG_ADDR (0x03006488)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_RESP_VC_SIZE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_RESP_VC_SIZE_REG_ADDR (0x03006490)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_TR_ID_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_TR_ID_REG_ADDR (0x03006498)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_TR_ID_BASE_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_TR_ID_BASE_REG_ADDR (0x030064A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_TR_ID_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_TR_ID_SIZE_REG_ADDR (0x030064A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_MCAST_EXCLUDE_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_MCAST_EXCLUDE_REG_ADDR (0x030064B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_SCATTER_LIST_ADDR_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_SCATTER_LIST_ADDR_REG_ADDR (0x030064B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_SCATTER_BASE_ADDR_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_SCATTER_BASE_ADDR_REG_ADDR (0x030064C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_SCATTER_INDEX_REG_OFFSET (0x000000C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_SCATTER_INDEX_REG_ADDR (0x030064C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_SCATTER_TIMES_REG_OFFSET (0x000000D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_SCATTER_TIMES_REG_ADDR (0x030064D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_SCATTER_ADDR_0__REG_OFFSET (0x000000D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_SCATTER_ADDR_0__REG_ADDR (0x030064D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_SCATTER_ADDR_1__REG_OFFSET (0x000000E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_SCATTER_ADDR_1__REG_ADDR (0x030064E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_SCATTER_ADDR_2__REG_OFFSET (0x000000E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_SCATTER_ADDR_2__REG_ADDR (0x030064E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_SCATTER_ADDR_3__REG_OFFSET (0x000000F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_SCATTER_ADDR_3__REG_ADDR (0x030064F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_INLINE_DATA_REG_OFFSET (0x000000F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_INLINE_DATA_REG_ADDR (0x030064F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_MAX_BYTES_IN_PACKET_REG_OFFSET (0x00000100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_MAX_BYTES_IN_PACKET_REG_ADDR (0x03006500)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_MCAST_DESTS_REG_OFFSET (0x00000108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_MCAST_DESTS_REG_ADDR (0x03006508)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_L1_ACCUM_CFG_REG_OFFSET (0x00000110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_L1_ACCUM_CFG_REG_ADDR (0x03006510)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_AXI_OPT_1_REG_OFFSET (0x00000118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_AXI_OPT_1_REG_ADDR (0x03006518)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_AXI_OPT_2_REG_OFFSET (0x00000120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_AXI_OPT_2_REG_ADDR (0x03006520)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_AUTOINC_REG_OFFSET (0x00000128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_AUTOINC_REG_ADDR (0x03006528)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_PACKET_TAGS_REG_OFFSET (0x00000130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_PACKET_TAGS_REG_ADDR (0x03006530)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_DEBUG_REG_OFFSET (0x00000138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_DEBUG_REG_ADDR (0x03006538)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_MISC_REG_OFFSET (0x00000140)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_R_MISC_REG_ADDR (0x03006540)

//==============================================================================
// Register File: tt_rocc_cpu3_cmd_buf_w
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_REG_FILE_BASE_ADDR (0x03006600)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_REG_FILE_SIZE (0x00000148)

#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_IE_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_IE_REG_ADDR (0x03006600)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_IP_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_IP_REG_ADDR (0x03006608)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_WR_SENT_TR_ID_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_WR_SENT_TR_ID_REG_ADDR (0x03006610)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_TR_ACK_TR_ID_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_TR_ACK_TR_ID_REG_ADDR (0x03006618)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_SRC_ADDR_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_SRC_ADDR_REG_ADDR (0x03006620)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_SRC_BASE_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_SRC_BASE_REG_ADDR (0x03006628)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_SRC_SIZE_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_SRC_SIZE_REG_ADDR (0x03006630)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_SRC_COORD_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_SRC_COORD_REG_ADDR (0x03006638)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_DEST_ADDR_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_DEST_ADDR_REG_ADDR (0x03006640)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_DEST_BASE_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_DEST_BASE_REG_ADDR (0x03006648)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_DEST_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_DEST_SIZE_REG_ADDR (0x03006650)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_DEST_COORD_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_DEST_COORD_REG_ADDR (0x03006658)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_LEN_BYTES_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_LEN_BYTES_REG_ADDR (0x03006660)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_REQ_VC_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_REQ_VC_REG_ADDR (0x03006668)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_REQ_VC_BASE_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_REQ_VC_BASE_REG_ADDR (0x03006670)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_REQ_VC_SIZE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_REQ_VC_SIZE_REG_ADDR (0x03006678)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_RESP_VC_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_RESP_VC_REG_ADDR (0x03006680)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_RESP_VC_BASE_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_RESP_VC_BASE_REG_ADDR (0x03006688)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_RESP_VC_SIZE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_RESP_VC_SIZE_REG_ADDR (0x03006690)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_TR_ID_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_TR_ID_REG_ADDR (0x03006698)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_TR_ID_BASE_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_TR_ID_BASE_REG_ADDR (0x030066A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_TR_ID_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_TR_ID_SIZE_REG_ADDR (0x030066A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_MCAST_EXCLUDE_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_MCAST_EXCLUDE_REG_ADDR (0x030066B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_SCATTER_LIST_ADDR_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_SCATTER_LIST_ADDR_REG_ADDR (0x030066B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_SCATTER_BASE_ADDR_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_SCATTER_BASE_ADDR_REG_ADDR (0x030066C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_SCATTER_INDEX_REG_OFFSET (0x000000C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_SCATTER_INDEX_REG_ADDR (0x030066C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_SCATTER_TIMES_REG_OFFSET (0x000000D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_SCATTER_TIMES_REG_ADDR (0x030066D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_SCATTER_ADDR_0__REG_OFFSET (0x000000D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_SCATTER_ADDR_0__REG_ADDR (0x030066D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_SCATTER_ADDR_1__REG_OFFSET (0x000000E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_SCATTER_ADDR_1__REG_ADDR (0x030066E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_SCATTER_ADDR_2__REG_OFFSET (0x000000E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_SCATTER_ADDR_2__REG_ADDR (0x030066E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_SCATTER_ADDR_3__REG_OFFSET (0x000000F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_SCATTER_ADDR_3__REG_ADDR (0x030066F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_INLINE_DATA_REG_OFFSET (0x000000F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_INLINE_DATA_REG_ADDR (0x030066F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_MAX_BYTES_IN_PACKET_REG_OFFSET (0x00000100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_MAX_BYTES_IN_PACKET_REG_ADDR (0x03006700)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_MCAST_DESTS_REG_OFFSET (0x00000108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_MCAST_DESTS_REG_ADDR (0x03006708)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_L1_ACCUM_CFG_REG_OFFSET (0x00000110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_L1_ACCUM_CFG_REG_ADDR (0x03006710)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_AXI_OPT_1_REG_OFFSET (0x00000118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_AXI_OPT_1_REG_ADDR (0x03006718)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_AXI_OPT_2_REG_OFFSET (0x00000120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_AXI_OPT_2_REG_ADDR (0x03006720)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_AUTOINC_REG_OFFSET (0x00000128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_AUTOINC_REG_ADDR (0x03006728)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_PACKET_TAGS_REG_OFFSET (0x00000130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_PACKET_TAGS_REG_ADDR (0x03006730)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_DEBUG_REG_OFFSET (0x00000138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_DEBUG_REG_ADDR (0x03006738)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_MISC_REG_OFFSET (0x00000140)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_CMD_BUF_W_MISC_REG_ADDR (0x03006740)

//==============================================================================
// Register File: tt_rocc_cpu3_address_gen_r
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_REG_FILE_BASE_ADDR (0x03006800)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_REG_FILE_SIZE (0x000000C8)

#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_SRC_BANK_CURRENT_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_SRC_BANK_CURRENT_REG_ADDR (0x03006800)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_SRC_BANK_BASE_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_SRC_BANK_BASE_REG_ADDR (0x03006808)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_SRC_BANK_SIZE_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_SRC_BANK_SIZE_REG_ADDR (0x03006810)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_SRC_BANK_SKIP_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_SRC_BANK_SKIP_REG_ADDR (0x03006818)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_SRC_INNER_STRIDE_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_SRC_INNER_STRIDE_REG_ADDR (0x03006820)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_SRC_INNER_END_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_SRC_INNER_END_REG_ADDR (0x03006828)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_SRC_INNER_ADDRESS_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_SRC_INNER_ADDRESS_REG_ADDR (0x03006830)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_SRC_OUTER_STRIDE_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_SRC_OUTER_STRIDE_REG_ADDR (0x03006838)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_SRC_OUTER_END_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_SRC_OUTER_END_REG_ADDR (0x03006840)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_SRC_OUTER_ADDRESS_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_SRC_OUTER_ADDRESS_REG_ADDR (0x03006848)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_SRC_FACE_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_SRC_FACE_SIZE_REG_ADDR (0x03006850)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_DEST_BANK_CURRENT_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_DEST_BANK_CURRENT_REG_ADDR (0x03006858)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_DEST_BANK_BASE_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_DEST_BANK_BASE_REG_ADDR (0x03006860)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_DEST_BANK_SIZE_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_DEST_BANK_SIZE_REG_ADDR (0x03006868)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_DEST_BANK_SKIP_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_DEST_BANK_SKIP_REG_ADDR (0x03006870)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_DEST_INNER_STRIDE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_DEST_INNER_STRIDE_REG_ADDR (0x03006878)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_DEST_INNER_END_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_DEST_INNER_END_REG_ADDR (0x03006880)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_DEST_INNER_ADDRESS_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_DEST_INNER_ADDRESS_REG_ADDR (0x03006888)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_DEST_OUTER_STRIDE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_DEST_OUTER_STRIDE_REG_ADDR (0x03006890)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_DEST_OUTER_END_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_DEST_OUTER_END_REG_ADDR (0x03006898)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_DEST_OUTER_ADDRESS_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_DEST_OUTER_ADDRESS_REG_ADDR (0x030068A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_DEST_FACE_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_DEST_FACE_SIZE_REG_ADDR (0x030068A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_SRC_GEN_ADDRESS_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_SRC_GEN_ADDRESS_REG_ADDR (0x030068B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_DEST_GEN_ADDRESS_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_DEST_GEN_ADDRESS_REG_ADDR (0x030068B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_MISC_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_R_MISC_REG_ADDR (0x030068C0)

//==============================================================================
// Register File: tt_rocc_cpu3_address_gen_w
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_REG_FILE_BASE_ADDR (0x03006A00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_REG_FILE_SIZE (0x000000C8)

#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_SRC_BANK_CURRENT_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_SRC_BANK_CURRENT_REG_ADDR (0x03006A00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_SRC_BANK_BASE_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_SRC_BANK_BASE_REG_ADDR (0x03006A08)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_SRC_BANK_SIZE_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_SRC_BANK_SIZE_REG_ADDR (0x03006A10)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_SRC_BANK_SKIP_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_SRC_BANK_SKIP_REG_ADDR (0x03006A18)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_SRC_INNER_STRIDE_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_SRC_INNER_STRIDE_REG_ADDR (0x03006A20)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_SRC_INNER_END_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_SRC_INNER_END_REG_ADDR (0x03006A28)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_SRC_INNER_ADDRESS_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_SRC_INNER_ADDRESS_REG_ADDR (0x03006A30)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_SRC_OUTER_STRIDE_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_SRC_OUTER_STRIDE_REG_ADDR (0x03006A38)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_SRC_OUTER_END_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_SRC_OUTER_END_REG_ADDR (0x03006A40)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_SRC_OUTER_ADDRESS_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_SRC_OUTER_ADDRESS_REG_ADDR (0x03006A48)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_SRC_FACE_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_SRC_FACE_SIZE_REG_ADDR (0x03006A50)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_DEST_BANK_CURRENT_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_DEST_BANK_CURRENT_REG_ADDR (0x03006A58)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_DEST_BANK_BASE_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_DEST_BANK_BASE_REG_ADDR (0x03006A60)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_DEST_BANK_SIZE_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_DEST_BANK_SIZE_REG_ADDR (0x03006A68)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_DEST_BANK_SKIP_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_DEST_BANK_SKIP_REG_ADDR (0x03006A70)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_DEST_INNER_STRIDE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_DEST_INNER_STRIDE_REG_ADDR (0x03006A78)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_DEST_INNER_END_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_DEST_INNER_END_REG_ADDR (0x03006A80)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_DEST_INNER_ADDRESS_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_DEST_INNER_ADDRESS_REG_ADDR (0x03006A88)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_DEST_OUTER_STRIDE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_DEST_OUTER_STRIDE_REG_ADDR (0x03006A90)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_DEST_OUTER_END_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_DEST_OUTER_END_REG_ADDR (0x03006A98)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_DEST_OUTER_ADDRESS_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_DEST_OUTER_ADDRESS_REG_ADDR (0x03006AA0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_DEST_FACE_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_DEST_FACE_SIZE_REG_ADDR (0x03006AA8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_SRC_GEN_ADDRESS_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_SRC_GEN_ADDRESS_REG_ADDR (0x03006AB0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_DEST_GEN_ADDRESS_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_DEST_GEN_ADDRESS_REG_ADDR (0x03006AB8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_MISC_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_ADDRESS_GEN_W_MISC_REG_ADDR (0x03006AC0)

//==============================================================================
// Register File: tt_rocc_cpu3_simple_cmd_buf
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_REG_FILE_BASE_ADDR (0x03006C00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_REG_FILE_SIZE (0x00000148)

#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_IE_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_IE_REG_ADDR (0x03006C00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_IP_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_IP_REG_ADDR (0x03006C08)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_0_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_0_REG_ADDR (0x03006C10)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_1_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_1_REG_ADDR (0x03006C18)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_SRC_ADDR_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_SRC_ADDR_REG_ADDR (0x03006C20)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_2_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_2_REG_ADDR (0x03006C28)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_3_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_3_REG_ADDR (0x03006C30)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_SRC_COORD_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_SRC_COORD_REG_ADDR (0x03006C38)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_DEST_ADDR_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_DEST_ADDR_REG_ADDR (0x03006C40)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_4_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_4_REG_ADDR (0x03006C48)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_5_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_5_REG_ADDR (0x03006C50)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_DEST_COORD_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_DEST_COORD_REG_ADDR (0x03006C58)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_LEN_BYTES_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_LEN_BYTES_REG_ADDR (0x03006C60)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_REQ_VC_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_REQ_VC_REG_ADDR (0x03006C68)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_6_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_6_REG_ADDR (0x03006C70)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_7_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_7_REG_ADDR (0x03006C78)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESP_VC_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESP_VC_REG_ADDR (0x03006C80)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_8_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_8_REG_ADDR (0x03006C88)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_9_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_9_REG_ADDR (0x03006C90)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_TR_ID_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_TR_ID_REG_ADDR (0x03006C98)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_10_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_10_REG_ADDR (0x03006CA0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_11_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_11_REG_ADDR (0x03006CA8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_MCAST_EXCLUDE_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_MCAST_EXCLUDE_REG_ADDR (0x03006CB0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_12_0__REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_12_0__REG_ADDR (0x03006CB8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_12_1__REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_12_1__REG_ADDR (0x03006CC0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_12_2__REG_OFFSET (0x000000C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_12_2__REG_ADDR (0x03006CC8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_12_3__REG_OFFSET (0x000000D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_12_3__REG_ADDR (0x03006CD0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_12_4__REG_OFFSET (0x000000D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_12_4__REG_ADDR (0x03006CD8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_12_5__REG_OFFSET (0x000000E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_12_5__REG_ADDR (0x03006CE0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_12_6__REG_OFFSET (0x000000E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_12_6__REG_ADDR (0x03006CE8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_12_7__REG_OFFSET (0x000000F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_12_7__REG_ADDR (0x03006CF0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_INLINE_DATA_REG_OFFSET (0x000000F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_INLINE_DATA_REG_ADDR (0x03006CF8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_13_REG_OFFSET (0x00000100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_13_REG_ADDR (0x03006D00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_MCAST_DESTS_REG_OFFSET (0x00000108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_MCAST_DESTS_REG_ADDR (0x03006D08)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_14_REG_OFFSET (0x00000110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_14_REG_ADDR (0x03006D10)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_15_REG_OFFSET (0x00000118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_15_REG_ADDR (0x03006D18)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_16_REG_OFFSET (0x00000120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_16_REG_ADDR (0x03006D20)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_17_REG_OFFSET (0x00000128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_RESERVED_17_REG_ADDR (0x03006D28)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_PACKET_TAGS_REG_OFFSET (0x00000130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_PACKET_TAGS_REG_ADDR (0x03006D30)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_DEBUG_REG_OFFSET (0x00000138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_DEBUG_REG_ADDR (0x03006D38)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_MISC_REG_OFFSET (0x00000140)
#define TT_ROCC_ACCEL_TT_ROCC_CPU3_SIMPLE_CMD_BUF_MISC_REG_ADDR (0x03006D40)

//==============================================================================
// Register File: tt_rocc_cpu4_cmd_buf_r
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_REG_FILE_BASE_ADDR (0x03007000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_REG_FILE_SIZE (0x00000148)

#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_IE_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_IE_REG_ADDR (0x03007000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_IP_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_IP_REG_ADDR (0x03007008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_WR_SENT_TR_ID_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_WR_SENT_TR_ID_REG_ADDR (0x03007010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_TR_ACK_TR_ID_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_TR_ACK_TR_ID_REG_ADDR (0x03007018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_SRC_ADDR_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_SRC_ADDR_REG_ADDR (0x03007020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_SRC_BASE_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_SRC_BASE_REG_ADDR (0x03007028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_SRC_SIZE_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_SRC_SIZE_REG_ADDR (0x03007030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_SRC_COORD_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_SRC_COORD_REG_ADDR (0x03007038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_DEST_ADDR_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_DEST_ADDR_REG_ADDR (0x03007040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_DEST_BASE_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_DEST_BASE_REG_ADDR (0x03007048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_DEST_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_DEST_SIZE_REG_ADDR (0x03007050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_DEST_COORD_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_DEST_COORD_REG_ADDR (0x03007058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_LEN_BYTES_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_LEN_BYTES_REG_ADDR (0x03007060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_REQ_VC_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_REQ_VC_REG_ADDR (0x03007068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_REQ_VC_BASE_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_REQ_VC_BASE_REG_ADDR (0x03007070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_REQ_VC_SIZE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_REQ_VC_SIZE_REG_ADDR (0x03007078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_RESP_VC_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_RESP_VC_REG_ADDR (0x03007080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_RESP_VC_BASE_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_RESP_VC_BASE_REG_ADDR (0x03007088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_RESP_VC_SIZE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_RESP_VC_SIZE_REG_ADDR (0x03007090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_TR_ID_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_TR_ID_REG_ADDR (0x03007098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_TR_ID_BASE_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_TR_ID_BASE_REG_ADDR (0x030070A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_TR_ID_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_TR_ID_SIZE_REG_ADDR (0x030070A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_MCAST_EXCLUDE_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_MCAST_EXCLUDE_REG_ADDR (0x030070B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_SCATTER_LIST_ADDR_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_SCATTER_LIST_ADDR_REG_ADDR (0x030070B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_SCATTER_BASE_ADDR_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_SCATTER_BASE_ADDR_REG_ADDR (0x030070C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_SCATTER_INDEX_REG_OFFSET (0x000000C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_SCATTER_INDEX_REG_ADDR (0x030070C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_SCATTER_TIMES_REG_OFFSET (0x000000D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_SCATTER_TIMES_REG_ADDR (0x030070D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_SCATTER_ADDR_0__REG_OFFSET (0x000000D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_SCATTER_ADDR_0__REG_ADDR (0x030070D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_SCATTER_ADDR_1__REG_OFFSET (0x000000E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_SCATTER_ADDR_1__REG_ADDR (0x030070E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_SCATTER_ADDR_2__REG_OFFSET (0x000000E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_SCATTER_ADDR_2__REG_ADDR (0x030070E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_SCATTER_ADDR_3__REG_OFFSET (0x000000F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_SCATTER_ADDR_3__REG_ADDR (0x030070F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_INLINE_DATA_REG_OFFSET (0x000000F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_INLINE_DATA_REG_ADDR (0x030070F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_MAX_BYTES_IN_PACKET_REG_OFFSET (0x00000100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_MAX_BYTES_IN_PACKET_REG_ADDR (0x03007100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_MCAST_DESTS_REG_OFFSET (0x00000108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_MCAST_DESTS_REG_ADDR (0x03007108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_L1_ACCUM_CFG_REG_OFFSET (0x00000110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_L1_ACCUM_CFG_REG_ADDR (0x03007110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_AXI_OPT_1_REG_OFFSET (0x00000118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_AXI_OPT_1_REG_ADDR (0x03007118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_AXI_OPT_2_REG_OFFSET (0x00000120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_AXI_OPT_2_REG_ADDR (0x03007120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_AUTOINC_REG_OFFSET (0x00000128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_AUTOINC_REG_ADDR (0x03007128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_PACKET_TAGS_REG_OFFSET (0x00000130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_PACKET_TAGS_REG_ADDR (0x03007130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_DEBUG_REG_OFFSET (0x00000138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_DEBUG_REG_ADDR (0x03007138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_MISC_REG_OFFSET (0x00000140)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_R_MISC_REG_ADDR (0x03007140)

//==============================================================================
// Register File: tt_rocc_cpu4_cmd_buf_w
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_REG_FILE_BASE_ADDR (0x03007200)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_REG_FILE_SIZE (0x00000148)

#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_IE_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_IE_REG_ADDR (0x03007200)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_IP_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_IP_REG_ADDR (0x03007208)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_WR_SENT_TR_ID_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_WR_SENT_TR_ID_REG_ADDR (0x03007210)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_TR_ACK_TR_ID_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_TR_ACK_TR_ID_REG_ADDR (0x03007218)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_SRC_ADDR_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_SRC_ADDR_REG_ADDR (0x03007220)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_SRC_BASE_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_SRC_BASE_REG_ADDR (0x03007228)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_SRC_SIZE_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_SRC_SIZE_REG_ADDR (0x03007230)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_SRC_COORD_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_SRC_COORD_REG_ADDR (0x03007238)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_DEST_ADDR_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_DEST_ADDR_REG_ADDR (0x03007240)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_DEST_BASE_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_DEST_BASE_REG_ADDR (0x03007248)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_DEST_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_DEST_SIZE_REG_ADDR (0x03007250)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_DEST_COORD_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_DEST_COORD_REG_ADDR (0x03007258)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_LEN_BYTES_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_LEN_BYTES_REG_ADDR (0x03007260)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_REQ_VC_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_REQ_VC_REG_ADDR (0x03007268)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_REQ_VC_BASE_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_REQ_VC_BASE_REG_ADDR (0x03007270)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_REQ_VC_SIZE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_REQ_VC_SIZE_REG_ADDR (0x03007278)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_RESP_VC_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_RESP_VC_REG_ADDR (0x03007280)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_RESP_VC_BASE_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_RESP_VC_BASE_REG_ADDR (0x03007288)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_RESP_VC_SIZE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_RESP_VC_SIZE_REG_ADDR (0x03007290)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_TR_ID_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_TR_ID_REG_ADDR (0x03007298)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_TR_ID_BASE_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_TR_ID_BASE_REG_ADDR (0x030072A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_TR_ID_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_TR_ID_SIZE_REG_ADDR (0x030072A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_MCAST_EXCLUDE_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_MCAST_EXCLUDE_REG_ADDR (0x030072B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_SCATTER_LIST_ADDR_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_SCATTER_LIST_ADDR_REG_ADDR (0x030072B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_SCATTER_BASE_ADDR_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_SCATTER_BASE_ADDR_REG_ADDR (0x030072C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_SCATTER_INDEX_REG_OFFSET (0x000000C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_SCATTER_INDEX_REG_ADDR (0x030072C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_SCATTER_TIMES_REG_OFFSET (0x000000D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_SCATTER_TIMES_REG_ADDR (0x030072D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_SCATTER_ADDR_0__REG_OFFSET (0x000000D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_SCATTER_ADDR_0__REG_ADDR (0x030072D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_SCATTER_ADDR_1__REG_OFFSET (0x000000E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_SCATTER_ADDR_1__REG_ADDR (0x030072E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_SCATTER_ADDR_2__REG_OFFSET (0x000000E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_SCATTER_ADDR_2__REG_ADDR (0x030072E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_SCATTER_ADDR_3__REG_OFFSET (0x000000F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_SCATTER_ADDR_3__REG_ADDR (0x030072F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_INLINE_DATA_REG_OFFSET (0x000000F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_INLINE_DATA_REG_ADDR (0x030072F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_MAX_BYTES_IN_PACKET_REG_OFFSET (0x00000100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_MAX_BYTES_IN_PACKET_REG_ADDR (0x03007300)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_MCAST_DESTS_REG_OFFSET (0x00000108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_MCAST_DESTS_REG_ADDR (0x03007308)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_L1_ACCUM_CFG_REG_OFFSET (0x00000110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_L1_ACCUM_CFG_REG_ADDR (0x03007310)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_AXI_OPT_1_REG_OFFSET (0x00000118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_AXI_OPT_1_REG_ADDR (0x03007318)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_AXI_OPT_2_REG_OFFSET (0x00000120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_AXI_OPT_2_REG_ADDR (0x03007320)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_AUTOINC_REG_OFFSET (0x00000128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_AUTOINC_REG_ADDR (0x03007328)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_PACKET_TAGS_REG_OFFSET (0x00000130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_PACKET_TAGS_REG_ADDR (0x03007330)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_DEBUG_REG_OFFSET (0x00000138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_DEBUG_REG_ADDR (0x03007338)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_MISC_REG_OFFSET (0x00000140)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_CMD_BUF_W_MISC_REG_ADDR (0x03007340)

//==============================================================================
// Register File: tt_rocc_cpu4_address_gen_r
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_REG_FILE_BASE_ADDR (0x03007400)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_REG_FILE_SIZE (0x000000C8)

#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_SRC_BANK_CURRENT_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_SRC_BANK_CURRENT_REG_ADDR (0x03007400)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_SRC_BANK_BASE_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_SRC_BANK_BASE_REG_ADDR (0x03007408)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_SRC_BANK_SIZE_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_SRC_BANK_SIZE_REG_ADDR (0x03007410)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_SRC_BANK_SKIP_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_SRC_BANK_SKIP_REG_ADDR (0x03007418)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_SRC_INNER_STRIDE_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_SRC_INNER_STRIDE_REG_ADDR (0x03007420)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_SRC_INNER_END_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_SRC_INNER_END_REG_ADDR (0x03007428)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_SRC_INNER_ADDRESS_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_SRC_INNER_ADDRESS_REG_ADDR (0x03007430)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_SRC_OUTER_STRIDE_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_SRC_OUTER_STRIDE_REG_ADDR (0x03007438)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_SRC_OUTER_END_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_SRC_OUTER_END_REG_ADDR (0x03007440)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_SRC_OUTER_ADDRESS_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_SRC_OUTER_ADDRESS_REG_ADDR (0x03007448)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_SRC_FACE_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_SRC_FACE_SIZE_REG_ADDR (0x03007450)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_DEST_BANK_CURRENT_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_DEST_BANK_CURRENT_REG_ADDR (0x03007458)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_DEST_BANK_BASE_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_DEST_BANK_BASE_REG_ADDR (0x03007460)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_DEST_BANK_SIZE_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_DEST_BANK_SIZE_REG_ADDR (0x03007468)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_DEST_BANK_SKIP_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_DEST_BANK_SKIP_REG_ADDR (0x03007470)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_DEST_INNER_STRIDE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_DEST_INNER_STRIDE_REG_ADDR (0x03007478)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_DEST_INNER_END_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_DEST_INNER_END_REG_ADDR (0x03007480)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_DEST_INNER_ADDRESS_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_DEST_INNER_ADDRESS_REG_ADDR (0x03007488)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_DEST_OUTER_STRIDE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_DEST_OUTER_STRIDE_REG_ADDR (0x03007490)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_DEST_OUTER_END_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_DEST_OUTER_END_REG_ADDR (0x03007498)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_DEST_OUTER_ADDRESS_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_DEST_OUTER_ADDRESS_REG_ADDR (0x030074A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_DEST_FACE_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_DEST_FACE_SIZE_REG_ADDR (0x030074A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_SRC_GEN_ADDRESS_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_SRC_GEN_ADDRESS_REG_ADDR (0x030074B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_DEST_GEN_ADDRESS_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_DEST_GEN_ADDRESS_REG_ADDR (0x030074B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_MISC_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_R_MISC_REG_ADDR (0x030074C0)

//==============================================================================
// Register File: tt_rocc_cpu4_address_gen_w
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_REG_FILE_BASE_ADDR (0x03007600)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_REG_FILE_SIZE (0x000000C8)

#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_SRC_BANK_CURRENT_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_SRC_BANK_CURRENT_REG_ADDR (0x03007600)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_SRC_BANK_BASE_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_SRC_BANK_BASE_REG_ADDR (0x03007608)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_SRC_BANK_SIZE_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_SRC_BANK_SIZE_REG_ADDR (0x03007610)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_SRC_BANK_SKIP_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_SRC_BANK_SKIP_REG_ADDR (0x03007618)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_SRC_INNER_STRIDE_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_SRC_INNER_STRIDE_REG_ADDR (0x03007620)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_SRC_INNER_END_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_SRC_INNER_END_REG_ADDR (0x03007628)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_SRC_INNER_ADDRESS_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_SRC_INNER_ADDRESS_REG_ADDR (0x03007630)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_SRC_OUTER_STRIDE_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_SRC_OUTER_STRIDE_REG_ADDR (0x03007638)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_SRC_OUTER_END_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_SRC_OUTER_END_REG_ADDR (0x03007640)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_SRC_OUTER_ADDRESS_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_SRC_OUTER_ADDRESS_REG_ADDR (0x03007648)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_SRC_FACE_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_SRC_FACE_SIZE_REG_ADDR (0x03007650)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_DEST_BANK_CURRENT_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_DEST_BANK_CURRENT_REG_ADDR (0x03007658)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_DEST_BANK_BASE_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_DEST_BANK_BASE_REG_ADDR (0x03007660)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_DEST_BANK_SIZE_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_DEST_BANK_SIZE_REG_ADDR (0x03007668)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_DEST_BANK_SKIP_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_DEST_BANK_SKIP_REG_ADDR (0x03007670)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_DEST_INNER_STRIDE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_DEST_INNER_STRIDE_REG_ADDR (0x03007678)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_DEST_INNER_END_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_DEST_INNER_END_REG_ADDR (0x03007680)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_DEST_INNER_ADDRESS_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_DEST_INNER_ADDRESS_REG_ADDR (0x03007688)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_DEST_OUTER_STRIDE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_DEST_OUTER_STRIDE_REG_ADDR (0x03007690)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_DEST_OUTER_END_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_DEST_OUTER_END_REG_ADDR (0x03007698)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_DEST_OUTER_ADDRESS_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_DEST_OUTER_ADDRESS_REG_ADDR (0x030076A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_DEST_FACE_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_DEST_FACE_SIZE_REG_ADDR (0x030076A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_SRC_GEN_ADDRESS_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_SRC_GEN_ADDRESS_REG_ADDR (0x030076B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_DEST_GEN_ADDRESS_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_DEST_GEN_ADDRESS_REG_ADDR (0x030076B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_MISC_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_ADDRESS_GEN_W_MISC_REG_ADDR (0x030076C0)

//==============================================================================
// Register File: tt_rocc_cpu4_simple_cmd_buf
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_REG_FILE_BASE_ADDR (0x03007800)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_REG_FILE_SIZE (0x00000148)

#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_IE_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_IE_REG_ADDR (0x03007800)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_IP_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_IP_REG_ADDR (0x03007808)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_0_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_0_REG_ADDR (0x03007810)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_1_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_1_REG_ADDR (0x03007818)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_SRC_ADDR_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_SRC_ADDR_REG_ADDR (0x03007820)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_2_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_2_REG_ADDR (0x03007828)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_3_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_3_REG_ADDR (0x03007830)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_SRC_COORD_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_SRC_COORD_REG_ADDR (0x03007838)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_DEST_ADDR_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_DEST_ADDR_REG_ADDR (0x03007840)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_4_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_4_REG_ADDR (0x03007848)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_5_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_5_REG_ADDR (0x03007850)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_DEST_COORD_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_DEST_COORD_REG_ADDR (0x03007858)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_LEN_BYTES_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_LEN_BYTES_REG_ADDR (0x03007860)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_REQ_VC_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_REQ_VC_REG_ADDR (0x03007868)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_6_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_6_REG_ADDR (0x03007870)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_7_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_7_REG_ADDR (0x03007878)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESP_VC_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESP_VC_REG_ADDR (0x03007880)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_8_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_8_REG_ADDR (0x03007888)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_9_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_9_REG_ADDR (0x03007890)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_TR_ID_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_TR_ID_REG_ADDR (0x03007898)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_10_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_10_REG_ADDR (0x030078A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_11_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_11_REG_ADDR (0x030078A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_MCAST_EXCLUDE_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_MCAST_EXCLUDE_REG_ADDR (0x030078B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_12_0__REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_12_0__REG_ADDR (0x030078B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_12_1__REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_12_1__REG_ADDR (0x030078C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_12_2__REG_OFFSET (0x000000C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_12_2__REG_ADDR (0x030078C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_12_3__REG_OFFSET (0x000000D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_12_3__REG_ADDR (0x030078D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_12_4__REG_OFFSET (0x000000D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_12_4__REG_ADDR (0x030078D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_12_5__REG_OFFSET (0x000000E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_12_5__REG_ADDR (0x030078E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_12_6__REG_OFFSET (0x000000E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_12_6__REG_ADDR (0x030078E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_12_7__REG_OFFSET (0x000000F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_12_7__REG_ADDR (0x030078F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_INLINE_DATA_REG_OFFSET (0x000000F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_INLINE_DATA_REG_ADDR (0x030078F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_13_REG_OFFSET (0x00000100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_13_REG_ADDR (0x03007900)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_MCAST_DESTS_REG_OFFSET (0x00000108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_MCAST_DESTS_REG_ADDR (0x03007908)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_14_REG_OFFSET (0x00000110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_14_REG_ADDR (0x03007910)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_15_REG_OFFSET (0x00000118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_15_REG_ADDR (0x03007918)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_16_REG_OFFSET (0x00000120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_16_REG_ADDR (0x03007920)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_17_REG_OFFSET (0x00000128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_RESERVED_17_REG_ADDR (0x03007928)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_PACKET_TAGS_REG_OFFSET (0x00000130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_PACKET_TAGS_REG_ADDR (0x03007930)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_DEBUG_REG_OFFSET (0x00000138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_DEBUG_REG_ADDR (0x03007938)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_MISC_REG_OFFSET (0x00000140)
#define TT_ROCC_ACCEL_TT_ROCC_CPU4_SIMPLE_CMD_BUF_MISC_REG_ADDR (0x03007940)

//==============================================================================
// Register File: tt_rocc_cpu5_cmd_buf_r
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_REG_FILE_BASE_ADDR (0x03007C00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_REG_FILE_SIZE (0x00000148)

#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_IE_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_IE_REG_ADDR (0x03007C00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_IP_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_IP_REG_ADDR (0x03007C08)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_WR_SENT_TR_ID_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_WR_SENT_TR_ID_REG_ADDR (0x03007C10)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_TR_ACK_TR_ID_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_TR_ACK_TR_ID_REG_ADDR (0x03007C18)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_SRC_ADDR_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_SRC_ADDR_REG_ADDR (0x03007C20)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_SRC_BASE_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_SRC_BASE_REG_ADDR (0x03007C28)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_SRC_SIZE_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_SRC_SIZE_REG_ADDR (0x03007C30)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_SRC_COORD_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_SRC_COORD_REG_ADDR (0x03007C38)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_DEST_ADDR_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_DEST_ADDR_REG_ADDR (0x03007C40)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_DEST_BASE_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_DEST_BASE_REG_ADDR (0x03007C48)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_DEST_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_DEST_SIZE_REG_ADDR (0x03007C50)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_DEST_COORD_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_DEST_COORD_REG_ADDR (0x03007C58)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_LEN_BYTES_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_LEN_BYTES_REG_ADDR (0x03007C60)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_REQ_VC_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_REQ_VC_REG_ADDR (0x03007C68)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_REQ_VC_BASE_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_REQ_VC_BASE_REG_ADDR (0x03007C70)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_REQ_VC_SIZE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_REQ_VC_SIZE_REG_ADDR (0x03007C78)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_RESP_VC_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_RESP_VC_REG_ADDR (0x03007C80)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_RESP_VC_BASE_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_RESP_VC_BASE_REG_ADDR (0x03007C88)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_RESP_VC_SIZE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_RESP_VC_SIZE_REG_ADDR (0x03007C90)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_TR_ID_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_TR_ID_REG_ADDR (0x03007C98)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_TR_ID_BASE_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_TR_ID_BASE_REG_ADDR (0x03007CA0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_TR_ID_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_TR_ID_SIZE_REG_ADDR (0x03007CA8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_MCAST_EXCLUDE_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_MCAST_EXCLUDE_REG_ADDR (0x03007CB0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_SCATTER_LIST_ADDR_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_SCATTER_LIST_ADDR_REG_ADDR (0x03007CB8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_SCATTER_BASE_ADDR_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_SCATTER_BASE_ADDR_REG_ADDR (0x03007CC0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_SCATTER_INDEX_REG_OFFSET (0x000000C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_SCATTER_INDEX_REG_ADDR (0x03007CC8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_SCATTER_TIMES_REG_OFFSET (0x000000D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_SCATTER_TIMES_REG_ADDR (0x03007CD0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_SCATTER_ADDR_0__REG_OFFSET (0x000000D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_SCATTER_ADDR_0__REG_ADDR (0x03007CD8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_SCATTER_ADDR_1__REG_OFFSET (0x000000E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_SCATTER_ADDR_1__REG_ADDR (0x03007CE0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_SCATTER_ADDR_2__REG_OFFSET (0x000000E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_SCATTER_ADDR_2__REG_ADDR (0x03007CE8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_SCATTER_ADDR_3__REG_OFFSET (0x000000F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_SCATTER_ADDR_3__REG_ADDR (0x03007CF0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_INLINE_DATA_REG_OFFSET (0x000000F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_INLINE_DATA_REG_ADDR (0x03007CF8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_MAX_BYTES_IN_PACKET_REG_OFFSET (0x00000100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_MAX_BYTES_IN_PACKET_REG_ADDR (0x03007D00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_MCAST_DESTS_REG_OFFSET (0x00000108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_MCAST_DESTS_REG_ADDR (0x03007D08)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_L1_ACCUM_CFG_REG_OFFSET (0x00000110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_L1_ACCUM_CFG_REG_ADDR (0x03007D10)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_AXI_OPT_1_REG_OFFSET (0x00000118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_AXI_OPT_1_REG_ADDR (0x03007D18)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_AXI_OPT_2_REG_OFFSET (0x00000120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_AXI_OPT_2_REG_ADDR (0x03007D20)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_AUTOINC_REG_OFFSET (0x00000128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_AUTOINC_REG_ADDR (0x03007D28)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_PACKET_TAGS_REG_OFFSET (0x00000130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_PACKET_TAGS_REG_ADDR (0x03007D30)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_DEBUG_REG_OFFSET (0x00000138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_DEBUG_REG_ADDR (0x03007D38)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_MISC_REG_OFFSET (0x00000140)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_R_MISC_REG_ADDR (0x03007D40)

//==============================================================================
// Register File: tt_rocc_cpu5_cmd_buf_w
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_REG_FILE_BASE_ADDR (0x03007E00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_REG_FILE_SIZE (0x00000148)

#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_IE_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_IE_REG_ADDR (0x03007E00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_IP_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_IP_REG_ADDR (0x03007E08)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_WR_SENT_TR_ID_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_WR_SENT_TR_ID_REG_ADDR (0x03007E10)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_TR_ACK_TR_ID_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_TR_ACK_TR_ID_REG_ADDR (0x03007E18)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_SRC_ADDR_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_SRC_ADDR_REG_ADDR (0x03007E20)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_SRC_BASE_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_SRC_BASE_REG_ADDR (0x03007E28)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_SRC_SIZE_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_SRC_SIZE_REG_ADDR (0x03007E30)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_SRC_COORD_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_SRC_COORD_REG_ADDR (0x03007E38)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_DEST_ADDR_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_DEST_ADDR_REG_ADDR (0x03007E40)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_DEST_BASE_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_DEST_BASE_REG_ADDR (0x03007E48)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_DEST_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_DEST_SIZE_REG_ADDR (0x03007E50)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_DEST_COORD_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_DEST_COORD_REG_ADDR (0x03007E58)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_LEN_BYTES_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_LEN_BYTES_REG_ADDR (0x03007E60)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_REQ_VC_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_REQ_VC_REG_ADDR (0x03007E68)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_REQ_VC_BASE_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_REQ_VC_BASE_REG_ADDR (0x03007E70)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_REQ_VC_SIZE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_REQ_VC_SIZE_REG_ADDR (0x03007E78)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_RESP_VC_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_RESP_VC_REG_ADDR (0x03007E80)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_RESP_VC_BASE_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_RESP_VC_BASE_REG_ADDR (0x03007E88)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_RESP_VC_SIZE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_RESP_VC_SIZE_REG_ADDR (0x03007E90)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_TR_ID_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_TR_ID_REG_ADDR (0x03007E98)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_TR_ID_BASE_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_TR_ID_BASE_REG_ADDR (0x03007EA0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_TR_ID_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_TR_ID_SIZE_REG_ADDR (0x03007EA8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_MCAST_EXCLUDE_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_MCAST_EXCLUDE_REG_ADDR (0x03007EB0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_SCATTER_LIST_ADDR_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_SCATTER_LIST_ADDR_REG_ADDR (0x03007EB8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_SCATTER_BASE_ADDR_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_SCATTER_BASE_ADDR_REG_ADDR (0x03007EC0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_SCATTER_INDEX_REG_OFFSET (0x000000C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_SCATTER_INDEX_REG_ADDR (0x03007EC8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_SCATTER_TIMES_REG_OFFSET (0x000000D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_SCATTER_TIMES_REG_ADDR (0x03007ED0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_SCATTER_ADDR_0__REG_OFFSET (0x000000D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_SCATTER_ADDR_0__REG_ADDR (0x03007ED8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_SCATTER_ADDR_1__REG_OFFSET (0x000000E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_SCATTER_ADDR_1__REG_ADDR (0x03007EE0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_SCATTER_ADDR_2__REG_OFFSET (0x000000E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_SCATTER_ADDR_2__REG_ADDR (0x03007EE8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_SCATTER_ADDR_3__REG_OFFSET (0x000000F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_SCATTER_ADDR_3__REG_ADDR (0x03007EF0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_INLINE_DATA_REG_OFFSET (0x000000F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_INLINE_DATA_REG_ADDR (0x03007EF8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_MAX_BYTES_IN_PACKET_REG_OFFSET (0x00000100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_MAX_BYTES_IN_PACKET_REG_ADDR (0x03007F00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_MCAST_DESTS_REG_OFFSET (0x00000108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_MCAST_DESTS_REG_ADDR (0x03007F08)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_L1_ACCUM_CFG_REG_OFFSET (0x00000110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_L1_ACCUM_CFG_REG_ADDR (0x03007F10)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_AXI_OPT_1_REG_OFFSET (0x00000118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_AXI_OPT_1_REG_ADDR (0x03007F18)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_AXI_OPT_2_REG_OFFSET (0x00000120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_AXI_OPT_2_REG_ADDR (0x03007F20)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_AUTOINC_REG_OFFSET (0x00000128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_AUTOINC_REG_ADDR (0x03007F28)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_PACKET_TAGS_REG_OFFSET (0x00000130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_PACKET_TAGS_REG_ADDR (0x03007F30)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_DEBUG_REG_OFFSET (0x00000138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_DEBUG_REG_ADDR (0x03007F38)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_MISC_REG_OFFSET (0x00000140)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_CMD_BUF_W_MISC_REG_ADDR (0x03007F40)

//==============================================================================
// Register File: tt_rocc_cpu5_address_gen_r
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_REG_FILE_BASE_ADDR (0x03008000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_REG_FILE_SIZE (0x000000C8)

#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_SRC_BANK_CURRENT_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_SRC_BANK_CURRENT_REG_ADDR (0x03008000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_SRC_BANK_BASE_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_SRC_BANK_BASE_REG_ADDR (0x03008008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_SRC_BANK_SIZE_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_SRC_BANK_SIZE_REG_ADDR (0x03008010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_SRC_BANK_SKIP_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_SRC_BANK_SKIP_REG_ADDR (0x03008018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_SRC_INNER_STRIDE_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_SRC_INNER_STRIDE_REG_ADDR (0x03008020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_SRC_INNER_END_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_SRC_INNER_END_REG_ADDR (0x03008028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_SRC_INNER_ADDRESS_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_SRC_INNER_ADDRESS_REG_ADDR (0x03008030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_SRC_OUTER_STRIDE_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_SRC_OUTER_STRIDE_REG_ADDR (0x03008038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_SRC_OUTER_END_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_SRC_OUTER_END_REG_ADDR (0x03008040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_SRC_OUTER_ADDRESS_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_SRC_OUTER_ADDRESS_REG_ADDR (0x03008048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_SRC_FACE_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_SRC_FACE_SIZE_REG_ADDR (0x03008050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_DEST_BANK_CURRENT_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_DEST_BANK_CURRENT_REG_ADDR (0x03008058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_DEST_BANK_BASE_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_DEST_BANK_BASE_REG_ADDR (0x03008060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_DEST_BANK_SIZE_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_DEST_BANK_SIZE_REG_ADDR (0x03008068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_DEST_BANK_SKIP_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_DEST_BANK_SKIP_REG_ADDR (0x03008070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_DEST_INNER_STRIDE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_DEST_INNER_STRIDE_REG_ADDR (0x03008078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_DEST_INNER_END_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_DEST_INNER_END_REG_ADDR (0x03008080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_DEST_INNER_ADDRESS_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_DEST_INNER_ADDRESS_REG_ADDR (0x03008088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_DEST_OUTER_STRIDE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_DEST_OUTER_STRIDE_REG_ADDR (0x03008090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_DEST_OUTER_END_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_DEST_OUTER_END_REG_ADDR (0x03008098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_DEST_OUTER_ADDRESS_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_DEST_OUTER_ADDRESS_REG_ADDR (0x030080A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_DEST_FACE_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_DEST_FACE_SIZE_REG_ADDR (0x030080A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_SRC_GEN_ADDRESS_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_SRC_GEN_ADDRESS_REG_ADDR (0x030080B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_DEST_GEN_ADDRESS_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_DEST_GEN_ADDRESS_REG_ADDR (0x030080B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_MISC_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_R_MISC_REG_ADDR (0x030080C0)

//==============================================================================
// Register File: tt_rocc_cpu5_address_gen_w
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_REG_FILE_BASE_ADDR (0x03008200)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_REG_FILE_SIZE (0x000000C8)

#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_SRC_BANK_CURRENT_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_SRC_BANK_CURRENT_REG_ADDR (0x03008200)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_SRC_BANK_BASE_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_SRC_BANK_BASE_REG_ADDR (0x03008208)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_SRC_BANK_SIZE_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_SRC_BANK_SIZE_REG_ADDR (0x03008210)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_SRC_BANK_SKIP_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_SRC_BANK_SKIP_REG_ADDR (0x03008218)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_SRC_INNER_STRIDE_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_SRC_INNER_STRIDE_REG_ADDR (0x03008220)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_SRC_INNER_END_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_SRC_INNER_END_REG_ADDR (0x03008228)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_SRC_INNER_ADDRESS_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_SRC_INNER_ADDRESS_REG_ADDR (0x03008230)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_SRC_OUTER_STRIDE_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_SRC_OUTER_STRIDE_REG_ADDR (0x03008238)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_SRC_OUTER_END_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_SRC_OUTER_END_REG_ADDR (0x03008240)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_SRC_OUTER_ADDRESS_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_SRC_OUTER_ADDRESS_REG_ADDR (0x03008248)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_SRC_FACE_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_SRC_FACE_SIZE_REG_ADDR (0x03008250)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_DEST_BANK_CURRENT_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_DEST_BANK_CURRENT_REG_ADDR (0x03008258)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_DEST_BANK_BASE_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_DEST_BANK_BASE_REG_ADDR (0x03008260)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_DEST_BANK_SIZE_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_DEST_BANK_SIZE_REG_ADDR (0x03008268)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_DEST_BANK_SKIP_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_DEST_BANK_SKIP_REG_ADDR (0x03008270)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_DEST_INNER_STRIDE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_DEST_INNER_STRIDE_REG_ADDR (0x03008278)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_DEST_INNER_END_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_DEST_INNER_END_REG_ADDR (0x03008280)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_DEST_INNER_ADDRESS_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_DEST_INNER_ADDRESS_REG_ADDR (0x03008288)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_DEST_OUTER_STRIDE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_DEST_OUTER_STRIDE_REG_ADDR (0x03008290)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_DEST_OUTER_END_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_DEST_OUTER_END_REG_ADDR (0x03008298)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_DEST_OUTER_ADDRESS_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_DEST_OUTER_ADDRESS_REG_ADDR (0x030082A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_DEST_FACE_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_DEST_FACE_SIZE_REG_ADDR (0x030082A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_SRC_GEN_ADDRESS_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_SRC_GEN_ADDRESS_REG_ADDR (0x030082B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_DEST_GEN_ADDRESS_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_DEST_GEN_ADDRESS_REG_ADDR (0x030082B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_MISC_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_ADDRESS_GEN_W_MISC_REG_ADDR (0x030082C0)

//==============================================================================
// Register File: tt_rocc_cpu5_simple_cmd_buf
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_REG_FILE_BASE_ADDR (0x03008400)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_REG_FILE_SIZE (0x00000148)

#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_IE_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_IE_REG_ADDR (0x03008400)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_IP_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_IP_REG_ADDR (0x03008408)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_0_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_0_REG_ADDR (0x03008410)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_1_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_1_REG_ADDR (0x03008418)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_SRC_ADDR_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_SRC_ADDR_REG_ADDR (0x03008420)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_2_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_2_REG_ADDR (0x03008428)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_3_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_3_REG_ADDR (0x03008430)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_SRC_COORD_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_SRC_COORD_REG_ADDR (0x03008438)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_DEST_ADDR_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_DEST_ADDR_REG_ADDR (0x03008440)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_4_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_4_REG_ADDR (0x03008448)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_5_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_5_REG_ADDR (0x03008450)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_DEST_COORD_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_DEST_COORD_REG_ADDR (0x03008458)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_LEN_BYTES_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_LEN_BYTES_REG_ADDR (0x03008460)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_REQ_VC_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_REQ_VC_REG_ADDR (0x03008468)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_6_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_6_REG_ADDR (0x03008470)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_7_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_7_REG_ADDR (0x03008478)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESP_VC_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESP_VC_REG_ADDR (0x03008480)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_8_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_8_REG_ADDR (0x03008488)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_9_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_9_REG_ADDR (0x03008490)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_TR_ID_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_TR_ID_REG_ADDR (0x03008498)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_10_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_10_REG_ADDR (0x030084A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_11_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_11_REG_ADDR (0x030084A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_MCAST_EXCLUDE_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_MCAST_EXCLUDE_REG_ADDR (0x030084B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_12_0__REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_12_0__REG_ADDR (0x030084B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_12_1__REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_12_1__REG_ADDR (0x030084C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_12_2__REG_OFFSET (0x000000C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_12_2__REG_ADDR (0x030084C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_12_3__REG_OFFSET (0x000000D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_12_3__REG_ADDR (0x030084D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_12_4__REG_OFFSET (0x000000D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_12_4__REG_ADDR (0x030084D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_12_5__REG_OFFSET (0x000000E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_12_5__REG_ADDR (0x030084E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_12_6__REG_OFFSET (0x000000E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_12_6__REG_ADDR (0x030084E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_12_7__REG_OFFSET (0x000000F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_12_7__REG_ADDR (0x030084F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_INLINE_DATA_REG_OFFSET (0x000000F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_INLINE_DATA_REG_ADDR (0x030084F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_13_REG_OFFSET (0x00000100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_13_REG_ADDR (0x03008500)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_MCAST_DESTS_REG_OFFSET (0x00000108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_MCAST_DESTS_REG_ADDR (0x03008508)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_14_REG_OFFSET (0x00000110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_14_REG_ADDR (0x03008510)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_15_REG_OFFSET (0x00000118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_15_REG_ADDR (0x03008518)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_16_REG_OFFSET (0x00000120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_16_REG_ADDR (0x03008520)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_17_REG_OFFSET (0x00000128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_RESERVED_17_REG_ADDR (0x03008528)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_PACKET_TAGS_REG_OFFSET (0x00000130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_PACKET_TAGS_REG_ADDR (0x03008530)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_DEBUG_REG_OFFSET (0x00000138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_DEBUG_REG_ADDR (0x03008538)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_MISC_REG_OFFSET (0x00000140)
#define TT_ROCC_ACCEL_TT_ROCC_CPU5_SIMPLE_CMD_BUF_MISC_REG_ADDR (0x03008540)

//==============================================================================
// Register File: tt_rocc_cpu6_cmd_buf_r
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_REG_FILE_BASE_ADDR (0x03008800)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_REG_FILE_SIZE (0x00000148)

#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_IE_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_IE_REG_ADDR (0x03008800)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_IP_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_IP_REG_ADDR (0x03008808)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_WR_SENT_TR_ID_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_WR_SENT_TR_ID_REG_ADDR (0x03008810)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_TR_ACK_TR_ID_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_TR_ACK_TR_ID_REG_ADDR (0x03008818)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_SRC_ADDR_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_SRC_ADDR_REG_ADDR (0x03008820)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_SRC_BASE_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_SRC_BASE_REG_ADDR (0x03008828)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_SRC_SIZE_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_SRC_SIZE_REG_ADDR (0x03008830)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_SRC_COORD_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_SRC_COORD_REG_ADDR (0x03008838)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_DEST_ADDR_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_DEST_ADDR_REG_ADDR (0x03008840)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_DEST_BASE_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_DEST_BASE_REG_ADDR (0x03008848)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_DEST_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_DEST_SIZE_REG_ADDR (0x03008850)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_DEST_COORD_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_DEST_COORD_REG_ADDR (0x03008858)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_LEN_BYTES_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_LEN_BYTES_REG_ADDR (0x03008860)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_REQ_VC_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_REQ_VC_REG_ADDR (0x03008868)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_REQ_VC_BASE_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_REQ_VC_BASE_REG_ADDR (0x03008870)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_REQ_VC_SIZE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_REQ_VC_SIZE_REG_ADDR (0x03008878)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_RESP_VC_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_RESP_VC_REG_ADDR (0x03008880)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_RESP_VC_BASE_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_RESP_VC_BASE_REG_ADDR (0x03008888)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_RESP_VC_SIZE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_RESP_VC_SIZE_REG_ADDR (0x03008890)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_TR_ID_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_TR_ID_REG_ADDR (0x03008898)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_TR_ID_BASE_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_TR_ID_BASE_REG_ADDR (0x030088A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_TR_ID_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_TR_ID_SIZE_REG_ADDR (0x030088A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_MCAST_EXCLUDE_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_MCAST_EXCLUDE_REG_ADDR (0x030088B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_SCATTER_LIST_ADDR_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_SCATTER_LIST_ADDR_REG_ADDR (0x030088B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_SCATTER_BASE_ADDR_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_SCATTER_BASE_ADDR_REG_ADDR (0x030088C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_SCATTER_INDEX_REG_OFFSET (0x000000C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_SCATTER_INDEX_REG_ADDR (0x030088C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_SCATTER_TIMES_REG_OFFSET (0x000000D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_SCATTER_TIMES_REG_ADDR (0x030088D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_SCATTER_ADDR_0__REG_OFFSET (0x000000D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_SCATTER_ADDR_0__REG_ADDR (0x030088D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_SCATTER_ADDR_1__REG_OFFSET (0x000000E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_SCATTER_ADDR_1__REG_ADDR (0x030088E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_SCATTER_ADDR_2__REG_OFFSET (0x000000E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_SCATTER_ADDR_2__REG_ADDR (0x030088E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_SCATTER_ADDR_3__REG_OFFSET (0x000000F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_SCATTER_ADDR_3__REG_ADDR (0x030088F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_INLINE_DATA_REG_OFFSET (0x000000F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_INLINE_DATA_REG_ADDR (0x030088F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_MAX_BYTES_IN_PACKET_REG_OFFSET (0x00000100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_MAX_BYTES_IN_PACKET_REG_ADDR (0x03008900)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_MCAST_DESTS_REG_OFFSET (0x00000108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_MCAST_DESTS_REG_ADDR (0x03008908)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_L1_ACCUM_CFG_REG_OFFSET (0x00000110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_L1_ACCUM_CFG_REG_ADDR (0x03008910)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_AXI_OPT_1_REG_OFFSET (0x00000118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_AXI_OPT_1_REG_ADDR (0x03008918)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_AXI_OPT_2_REG_OFFSET (0x00000120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_AXI_OPT_2_REG_ADDR (0x03008920)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_AUTOINC_REG_OFFSET (0x00000128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_AUTOINC_REG_ADDR (0x03008928)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_PACKET_TAGS_REG_OFFSET (0x00000130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_PACKET_TAGS_REG_ADDR (0x03008930)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_DEBUG_REG_OFFSET (0x00000138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_DEBUG_REG_ADDR (0x03008938)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_MISC_REG_OFFSET (0x00000140)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_R_MISC_REG_ADDR (0x03008940)

//==============================================================================
// Register File: tt_rocc_cpu6_cmd_buf_w
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_REG_FILE_BASE_ADDR (0x03008A00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_REG_FILE_SIZE (0x00000148)

#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_IE_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_IE_REG_ADDR (0x03008A00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_IP_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_IP_REG_ADDR (0x03008A08)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_WR_SENT_TR_ID_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_WR_SENT_TR_ID_REG_ADDR (0x03008A10)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_TR_ACK_TR_ID_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_TR_ACK_TR_ID_REG_ADDR (0x03008A18)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_SRC_ADDR_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_SRC_ADDR_REG_ADDR (0x03008A20)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_SRC_BASE_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_SRC_BASE_REG_ADDR (0x03008A28)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_SRC_SIZE_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_SRC_SIZE_REG_ADDR (0x03008A30)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_SRC_COORD_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_SRC_COORD_REG_ADDR (0x03008A38)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_DEST_ADDR_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_DEST_ADDR_REG_ADDR (0x03008A40)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_DEST_BASE_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_DEST_BASE_REG_ADDR (0x03008A48)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_DEST_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_DEST_SIZE_REG_ADDR (0x03008A50)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_DEST_COORD_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_DEST_COORD_REG_ADDR (0x03008A58)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_LEN_BYTES_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_LEN_BYTES_REG_ADDR (0x03008A60)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_REQ_VC_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_REQ_VC_REG_ADDR (0x03008A68)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_REQ_VC_BASE_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_REQ_VC_BASE_REG_ADDR (0x03008A70)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_REQ_VC_SIZE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_REQ_VC_SIZE_REG_ADDR (0x03008A78)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_RESP_VC_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_RESP_VC_REG_ADDR (0x03008A80)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_RESP_VC_BASE_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_RESP_VC_BASE_REG_ADDR (0x03008A88)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_RESP_VC_SIZE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_RESP_VC_SIZE_REG_ADDR (0x03008A90)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_TR_ID_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_TR_ID_REG_ADDR (0x03008A98)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_TR_ID_BASE_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_TR_ID_BASE_REG_ADDR (0x03008AA0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_TR_ID_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_TR_ID_SIZE_REG_ADDR (0x03008AA8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_MCAST_EXCLUDE_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_MCAST_EXCLUDE_REG_ADDR (0x03008AB0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_SCATTER_LIST_ADDR_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_SCATTER_LIST_ADDR_REG_ADDR (0x03008AB8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_SCATTER_BASE_ADDR_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_SCATTER_BASE_ADDR_REG_ADDR (0x03008AC0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_SCATTER_INDEX_REG_OFFSET (0x000000C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_SCATTER_INDEX_REG_ADDR (0x03008AC8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_SCATTER_TIMES_REG_OFFSET (0x000000D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_SCATTER_TIMES_REG_ADDR (0x03008AD0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_SCATTER_ADDR_0__REG_OFFSET (0x000000D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_SCATTER_ADDR_0__REG_ADDR (0x03008AD8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_SCATTER_ADDR_1__REG_OFFSET (0x000000E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_SCATTER_ADDR_1__REG_ADDR (0x03008AE0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_SCATTER_ADDR_2__REG_OFFSET (0x000000E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_SCATTER_ADDR_2__REG_ADDR (0x03008AE8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_SCATTER_ADDR_3__REG_OFFSET (0x000000F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_SCATTER_ADDR_3__REG_ADDR (0x03008AF0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_INLINE_DATA_REG_OFFSET (0x000000F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_INLINE_DATA_REG_ADDR (0x03008AF8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_MAX_BYTES_IN_PACKET_REG_OFFSET (0x00000100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_MAX_BYTES_IN_PACKET_REG_ADDR (0x03008B00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_MCAST_DESTS_REG_OFFSET (0x00000108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_MCAST_DESTS_REG_ADDR (0x03008B08)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_L1_ACCUM_CFG_REG_OFFSET (0x00000110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_L1_ACCUM_CFG_REG_ADDR (0x03008B10)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_AXI_OPT_1_REG_OFFSET (0x00000118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_AXI_OPT_1_REG_ADDR (0x03008B18)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_AXI_OPT_2_REG_OFFSET (0x00000120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_AXI_OPT_2_REG_ADDR (0x03008B20)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_AUTOINC_REG_OFFSET (0x00000128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_AUTOINC_REG_ADDR (0x03008B28)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_PACKET_TAGS_REG_OFFSET (0x00000130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_PACKET_TAGS_REG_ADDR (0x03008B30)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_DEBUG_REG_OFFSET (0x00000138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_DEBUG_REG_ADDR (0x03008B38)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_MISC_REG_OFFSET (0x00000140)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_CMD_BUF_W_MISC_REG_ADDR (0x03008B40)

//==============================================================================
// Register File: tt_rocc_cpu6_address_gen_r
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_REG_FILE_BASE_ADDR (0x03008C00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_REG_FILE_SIZE (0x000000C8)

#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_SRC_BANK_CURRENT_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_SRC_BANK_CURRENT_REG_ADDR (0x03008C00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_SRC_BANK_BASE_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_SRC_BANK_BASE_REG_ADDR (0x03008C08)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_SRC_BANK_SIZE_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_SRC_BANK_SIZE_REG_ADDR (0x03008C10)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_SRC_BANK_SKIP_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_SRC_BANK_SKIP_REG_ADDR (0x03008C18)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_SRC_INNER_STRIDE_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_SRC_INNER_STRIDE_REG_ADDR (0x03008C20)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_SRC_INNER_END_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_SRC_INNER_END_REG_ADDR (0x03008C28)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_SRC_INNER_ADDRESS_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_SRC_INNER_ADDRESS_REG_ADDR (0x03008C30)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_SRC_OUTER_STRIDE_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_SRC_OUTER_STRIDE_REG_ADDR (0x03008C38)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_SRC_OUTER_END_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_SRC_OUTER_END_REG_ADDR (0x03008C40)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_SRC_OUTER_ADDRESS_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_SRC_OUTER_ADDRESS_REG_ADDR (0x03008C48)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_SRC_FACE_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_SRC_FACE_SIZE_REG_ADDR (0x03008C50)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_DEST_BANK_CURRENT_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_DEST_BANK_CURRENT_REG_ADDR (0x03008C58)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_DEST_BANK_BASE_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_DEST_BANK_BASE_REG_ADDR (0x03008C60)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_DEST_BANK_SIZE_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_DEST_BANK_SIZE_REG_ADDR (0x03008C68)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_DEST_BANK_SKIP_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_DEST_BANK_SKIP_REG_ADDR (0x03008C70)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_DEST_INNER_STRIDE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_DEST_INNER_STRIDE_REG_ADDR (0x03008C78)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_DEST_INNER_END_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_DEST_INNER_END_REG_ADDR (0x03008C80)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_DEST_INNER_ADDRESS_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_DEST_INNER_ADDRESS_REG_ADDR (0x03008C88)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_DEST_OUTER_STRIDE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_DEST_OUTER_STRIDE_REG_ADDR (0x03008C90)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_DEST_OUTER_END_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_DEST_OUTER_END_REG_ADDR (0x03008C98)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_DEST_OUTER_ADDRESS_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_DEST_OUTER_ADDRESS_REG_ADDR (0x03008CA0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_DEST_FACE_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_DEST_FACE_SIZE_REG_ADDR (0x03008CA8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_SRC_GEN_ADDRESS_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_SRC_GEN_ADDRESS_REG_ADDR (0x03008CB0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_DEST_GEN_ADDRESS_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_DEST_GEN_ADDRESS_REG_ADDR (0x03008CB8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_MISC_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_R_MISC_REG_ADDR (0x03008CC0)

//==============================================================================
// Register File: tt_rocc_cpu6_address_gen_w
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_REG_FILE_BASE_ADDR (0x03008E00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_REG_FILE_SIZE (0x000000C8)

#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_SRC_BANK_CURRENT_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_SRC_BANK_CURRENT_REG_ADDR (0x03008E00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_SRC_BANK_BASE_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_SRC_BANK_BASE_REG_ADDR (0x03008E08)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_SRC_BANK_SIZE_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_SRC_BANK_SIZE_REG_ADDR (0x03008E10)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_SRC_BANK_SKIP_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_SRC_BANK_SKIP_REG_ADDR (0x03008E18)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_SRC_INNER_STRIDE_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_SRC_INNER_STRIDE_REG_ADDR (0x03008E20)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_SRC_INNER_END_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_SRC_INNER_END_REG_ADDR (0x03008E28)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_SRC_INNER_ADDRESS_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_SRC_INNER_ADDRESS_REG_ADDR (0x03008E30)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_SRC_OUTER_STRIDE_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_SRC_OUTER_STRIDE_REG_ADDR (0x03008E38)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_SRC_OUTER_END_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_SRC_OUTER_END_REG_ADDR (0x03008E40)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_SRC_OUTER_ADDRESS_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_SRC_OUTER_ADDRESS_REG_ADDR (0x03008E48)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_SRC_FACE_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_SRC_FACE_SIZE_REG_ADDR (0x03008E50)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_DEST_BANK_CURRENT_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_DEST_BANK_CURRENT_REG_ADDR (0x03008E58)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_DEST_BANK_BASE_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_DEST_BANK_BASE_REG_ADDR (0x03008E60)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_DEST_BANK_SIZE_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_DEST_BANK_SIZE_REG_ADDR (0x03008E68)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_DEST_BANK_SKIP_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_DEST_BANK_SKIP_REG_ADDR (0x03008E70)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_DEST_INNER_STRIDE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_DEST_INNER_STRIDE_REG_ADDR (0x03008E78)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_DEST_INNER_END_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_DEST_INNER_END_REG_ADDR (0x03008E80)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_DEST_INNER_ADDRESS_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_DEST_INNER_ADDRESS_REG_ADDR (0x03008E88)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_DEST_OUTER_STRIDE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_DEST_OUTER_STRIDE_REG_ADDR (0x03008E90)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_DEST_OUTER_END_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_DEST_OUTER_END_REG_ADDR (0x03008E98)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_DEST_OUTER_ADDRESS_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_DEST_OUTER_ADDRESS_REG_ADDR (0x03008EA0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_DEST_FACE_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_DEST_FACE_SIZE_REG_ADDR (0x03008EA8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_SRC_GEN_ADDRESS_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_SRC_GEN_ADDRESS_REG_ADDR (0x03008EB0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_DEST_GEN_ADDRESS_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_DEST_GEN_ADDRESS_REG_ADDR (0x03008EB8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_MISC_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_ADDRESS_GEN_W_MISC_REG_ADDR (0x03008EC0)

//==============================================================================
// Register File: tt_rocc_cpu6_simple_cmd_buf
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_REG_FILE_BASE_ADDR (0x03009000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_REG_FILE_SIZE (0x00000148)

#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_IE_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_IE_REG_ADDR (0x03009000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_IP_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_IP_REG_ADDR (0x03009008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_0_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_0_REG_ADDR (0x03009010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_1_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_1_REG_ADDR (0x03009018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_SRC_ADDR_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_SRC_ADDR_REG_ADDR (0x03009020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_2_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_2_REG_ADDR (0x03009028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_3_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_3_REG_ADDR (0x03009030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_SRC_COORD_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_SRC_COORD_REG_ADDR (0x03009038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_DEST_ADDR_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_DEST_ADDR_REG_ADDR (0x03009040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_4_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_4_REG_ADDR (0x03009048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_5_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_5_REG_ADDR (0x03009050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_DEST_COORD_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_DEST_COORD_REG_ADDR (0x03009058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_LEN_BYTES_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_LEN_BYTES_REG_ADDR (0x03009060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_REQ_VC_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_REQ_VC_REG_ADDR (0x03009068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_6_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_6_REG_ADDR (0x03009070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_7_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_7_REG_ADDR (0x03009078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESP_VC_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESP_VC_REG_ADDR (0x03009080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_8_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_8_REG_ADDR (0x03009088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_9_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_9_REG_ADDR (0x03009090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_TR_ID_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_TR_ID_REG_ADDR (0x03009098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_10_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_10_REG_ADDR (0x030090A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_11_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_11_REG_ADDR (0x030090A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_MCAST_EXCLUDE_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_MCAST_EXCLUDE_REG_ADDR (0x030090B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_12_0__REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_12_0__REG_ADDR (0x030090B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_12_1__REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_12_1__REG_ADDR (0x030090C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_12_2__REG_OFFSET (0x000000C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_12_2__REG_ADDR (0x030090C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_12_3__REG_OFFSET (0x000000D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_12_3__REG_ADDR (0x030090D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_12_4__REG_OFFSET (0x000000D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_12_4__REG_ADDR (0x030090D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_12_5__REG_OFFSET (0x000000E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_12_5__REG_ADDR (0x030090E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_12_6__REG_OFFSET (0x000000E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_12_6__REG_ADDR (0x030090E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_12_7__REG_OFFSET (0x000000F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_12_7__REG_ADDR (0x030090F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_INLINE_DATA_REG_OFFSET (0x000000F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_INLINE_DATA_REG_ADDR (0x030090F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_13_REG_OFFSET (0x00000100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_13_REG_ADDR (0x03009100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_MCAST_DESTS_REG_OFFSET (0x00000108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_MCAST_DESTS_REG_ADDR (0x03009108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_14_REG_OFFSET (0x00000110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_14_REG_ADDR (0x03009110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_15_REG_OFFSET (0x00000118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_15_REG_ADDR (0x03009118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_16_REG_OFFSET (0x00000120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_16_REG_ADDR (0x03009120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_17_REG_OFFSET (0x00000128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_RESERVED_17_REG_ADDR (0x03009128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_PACKET_TAGS_REG_OFFSET (0x00000130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_PACKET_TAGS_REG_ADDR (0x03009130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_DEBUG_REG_OFFSET (0x00000138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_DEBUG_REG_ADDR (0x03009138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_MISC_REG_OFFSET (0x00000140)
#define TT_ROCC_ACCEL_TT_ROCC_CPU6_SIMPLE_CMD_BUF_MISC_REG_ADDR (0x03009140)

//==============================================================================
// Register File: tt_rocc_cpu7_cmd_buf_r
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_REG_FILE_BASE_ADDR (0x03009400)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_REG_FILE_SIZE (0x00000148)

#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_IE_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_IE_REG_ADDR (0x03009400)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_IP_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_IP_REG_ADDR (0x03009408)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_WR_SENT_TR_ID_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_WR_SENT_TR_ID_REG_ADDR (0x03009410)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_TR_ACK_TR_ID_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_TR_ACK_TR_ID_REG_ADDR (0x03009418)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_SRC_ADDR_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_SRC_ADDR_REG_ADDR (0x03009420)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_SRC_BASE_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_SRC_BASE_REG_ADDR (0x03009428)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_SRC_SIZE_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_SRC_SIZE_REG_ADDR (0x03009430)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_SRC_COORD_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_SRC_COORD_REG_ADDR (0x03009438)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_DEST_ADDR_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_DEST_ADDR_REG_ADDR (0x03009440)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_DEST_BASE_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_DEST_BASE_REG_ADDR (0x03009448)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_DEST_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_DEST_SIZE_REG_ADDR (0x03009450)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_DEST_COORD_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_DEST_COORD_REG_ADDR (0x03009458)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_LEN_BYTES_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_LEN_BYTES_REG_ADDR (0x03009460)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_REQ_VC_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_REQ_VC_REG_ADDR (0x03009468)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_REQ_VC_BASE_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_REQ_VC_BASE_REG_ADDR (0x03009470)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_REQ_VC_SIZE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_REQ_VC_SIZE_REG_ADDR (0x03009478)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_RESP_VC_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_RESP_VC_REG_ADDR (0x03009480)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_RESP_VC_BASE_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_RESP_VC_BASE_REG_ADDR (0x03009488)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_RESP_VC_SIZE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_RESP_VC_SIZE_REG_ADDR (0x03009490)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_TR_ID_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_TR_ID_REG_ADDR (0x03009498)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_TR_ID_BASE_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_TR_ID_BASE_REG_ADDR (0x030094A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_TR_ID_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_TR_ID_SIZE_REG_ADDR (0x030094A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_MCAST_EXCLUDE_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_MCAST_EXCLUDE_REG_ADDR (0x030094B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_SCATTER_LIST_ADDR_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_SCATTER_LIST_ADDR_REG_ADDR (0x030094B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_SCATTER_BASE_ADDR_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_SCATTER_BASE_ADDR_REG_ADDR (0x030094C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_SCATTER_INDEX_REG_OFFSET (0x000000C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_SCATTER_INDEX_REG_ADDR (0x030094C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_SCATTER_TIMES_REG_OFFSET (0x000000D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_SCATTER_TIMES_REG_ADDR (0x030094D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_SCATTER_ADDR_0__REG_OFFSET (0x000000D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_SCATTER_ADDR_0__REG_ADDR (0x030094D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_SCATTER_ADDR_1__REG_OFFSET (0x000000E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_SCATTER_ADDR_1__REG_ADDR (0x030094E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_SCATTER_ADDR_2__REG_OFFSET (0x000000E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_SCATTER_ADDR_2__REG_ADDR (0x030094E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_SCATTER_ADDR_3__REG_OFFSET (0x000000F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_SCATTER_ADDR_3__REG_ADDR (0x030094F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_INLINE_DATA_REG_OFFSET (0x000000F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_INLINE_DATA_REG_ADDR (0x030094F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_MAX_BYTES_IN_PACKET_REG_OFFSET (0x00000100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_MAX_BYTES_IN_PACKET_REG_ADDR (0x03009500)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_MCAST_DESTS_REG_OFFSET (0x00000108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_MCAST_DESTS_REG_ADDR (0x03009508)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_L1_ACCUM_CFG_REG_OFFSET (0x00000110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_L1_ACCUM_CFG_REG_ADDR (0x03009510)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_AXI_OPT_1_REG_OFFSET (0x00000118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_AXI_OPT_1_REG_ADDR (0x03009518)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_AXI_OPT_2_REG_OFFSET (0x00000120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_AXI_OPT_2_REG_ADDR (0x03009520)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_AUTOINC_REG_OFFSET (0x00000128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_AUTOINC_REG_ADDR (0x03009528)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_PACKET_TAGS_REG_OFFSET (0x00000130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_PACKET_TAGS_REG_ADDR (0x03009530)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_DEBUG_REG_OFFSET (0x00000138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_DEBUG_REG_ADDR (0x03009538)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_MISC_REG_OFFSET (0x00000140)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_R_MISC_REG_ADDR (0x03009540)

//==============================================================================
// Register File: tt_rocc_cpu7_cmd_buf_w
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_REG_FILE_BASE_ADDR (0x03009600)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_REG_FILE_SIZE (0x00000148)

#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_IE_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_IE_REG_ADDR (0x03009600)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_IP_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_IP_REG_ADDR (0x03009608)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_WR_SENT_TR_ID_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_WR_SENT_TR_ID_REG_ADDR (0x03009610)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_TR_ACK_TR_ID_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_TR_ACK_TR_ID_REG_ADDR (0x03009618)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_SRC_ADDR_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_SRC_ADDR_REG_ADDR (0x03009620)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_SRC_BASE_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_SRC_BASE_REG_ADDR (0x03009628)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_SRC_SIZE_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_SRC_SIZE_REG_ADDR (0x03009630)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_SRC_COORD_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_SRC_COORD_REG_ADDR (0x03009638)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_DEST_ADDR_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_DEST_ADDR_REG_ADDR (0x03009640)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_DEST_BASE_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_DEST_BASE_REG_ADDR (0x03009648)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_DEST_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_DEST_SIZE_REG_ADDR (0x03009650)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_DEST_COORD_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_DEST_COORD_REG_ADDR (0x03009658)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_LEN_BYTES_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_LEN_BYTES_REG_ADDR (0x03009660)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_REQ_VC_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_REQ_VC_REG_ADDR (0x03009668)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_REQ_VC_BASE_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_REQ_VC_BASE_REG_ADDR (0x03009670)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_REQ_VC_SIZE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_REQ_VC_SIZE_REG_ADDR (0x03009678)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_RESP_VC_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_RESP_VC_REG_ADDR (0x03009680)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_RESP_VC_BASE_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_RESP_VC_BASE_REG_ADDR (0x03009688)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_RESP_VC_SIZE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_RESP_VC_SIZE_REG_ADDR (0x03009690)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_TR_ID_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_TR_ID_REG_ADDR (0x03009698)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_TR_ID_BASE_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_TR_ID_BASE_REG_ADDR (0x030096A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_TR_ID_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_TR_ID_SIZE_REG_ADDR (0x030096A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_MCAST_EXCLUDE_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_MCAST_EXCLUDE_REG_ADDR (0x030096B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_SCATTER_LIST_ADDR_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_SCATTER_LIST_ADDR_REG_ADDR (0x030096B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_SCATTER_BASE_ADDR_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_SCATTER_BASE_ADDR_REG_ADDR (0x030096C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_SCATTER_INDEX_REG_OFFSET (0x000000C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_SCATTER_INDEX_REG_ADDR (0x030096C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_SCATTER_TIMES_REG_OFFSET (0x000000D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_SCATTER_TIMES_REG_ADDR (0x030096D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_SCATTER_ADDR_0__REG_OFFSET (0x000000D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_SCATTER_ADDR_0__REG_ADDR (0x030096D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_SCATTER_ADDR_1__REG_OFFSET (0x000000E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_SCATTER_ADDR_1__REG_ADDR (0x030096E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_SCATTER_ADDR_2__REG_OFFSET (0x000000E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_SCATTER_ADDR_2__REG_ADDR (0x030096E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_SCATTER_ADDR_3__REG_OFFSET (0x000000F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_SCATTER_ADDR_3__REG_ADDR (0x030096F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_INLINE_DATA_REG_OFFSET (0x000000F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_INLINE_DATA_REG_ADDR (0x030096F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_MAX_BYTES_IN_PACKET_REG_OFFSET (0x00000100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_MAX_BYTES_IN_PACKET_REG_ADDR (0x03009700)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_MCAST_DESTS_REG_OFFSET (0x00000108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_MCAST_DESTS_REG_ADDR (0x03009708)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_L1_ACCUM_CFG_REG_OFFSET (0x00000110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_L1_ACCUM_CFG_REG_ADDR (0x03009710)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_AXI_OPT_1_REG_OFFSET (0x00000118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_AXI_OPT_1_REG_ADDR (0x03009718)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_AXI_OPT_2_REG_OFFSET (0x00000120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_AXI_OPT_2_REG_ADDR (0x03009720)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_AUTOINC_REG_OFFSET (0x00000128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_AUTOINC_REG_ADDR (0x03009728)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_PACKET_TAGS_REG_OFFSET (0x00000130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_PACKET_TAGS_REG_ADDR (0x03009730)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_DEBUG_REG_OFFSET (0x00000138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_DEBUG_REG_ADDR (0x03009738)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_MISC_REG_OFFSET (0x00000140)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_CMD_BUF_W_MISC_REG_ADDR (0x03009740)

//==============================================================================
// Register File: tt_rocc_cpu7_address_gen_r
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_REG_FILE_BASE_ADDR (0x03009800)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_REG_FILE_SIZE (0x000000C8)

#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_SRC_BANK_CURRENT_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_SRC_BANK_CURRENT_REG_ADDR (0x03009800)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_SRC_BANK_BASE_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_SRC_BANK_BASE_REG_ADDR (0x03009808)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_SRC_BANK_SIZE_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_SRC_BANK_SIZE_REG_ADDR (0x03009810)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_SRC_BANK_SKIP_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_SRC_BANK_SKIP_REG_ADDR (0x03009818)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_SRC_INNER_STRIDE_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_SRC_INNER_STRIDE_REG_ADDR (0x03009820)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_SRC_INNER_END_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_SRC_INNER_END_REG_ADDR (0x03009828)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_SRC_INNER_ADDRESS_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_SRC_INNER_ADDRESS_REG_ADDR (0x03009830)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_SRC_OUTER_STRIDE_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_SRC_OUTER_STRIDE_REG_ADDR (0x03009838)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_SRC_OUTER_END_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_SRC_OUTER_END_REG_ADDR (0x03009840)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_SRC_OUTER_ADDRESS_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_SRC_OUTER_ADDRESS_REG_ADDR (0x03009848)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_SRC_FACE_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_SRC_FACE_SIZE_REG_ADDR (0x03009850)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_DEST_BANK_CURRENT_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_DEST_BANK_CURRENT_REG_ADDR (0x03009858)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_DEST_BANK_BASE_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_DEST_BANK_BASE_REG_ADDR (0x03009860)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_DEST_BANK_SIZE_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_DEST_BANK_SIZE_REG_ADDR (0x03009868)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_DEST_BANK_SKIP_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_DEST_BANK_SKIP_REG_ADDR (0x03009870)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_DEST_INNER_STRIDE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_DEST_INNER_STRIDE_REG_ADDR (0x03009878)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_DEST_INNER_END_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_DEST_INNER_END_REG_ADDR (0x03009880)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_DEST_INNER_ADDRESS_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_DEST_INNER_ADDRESS_REG_ADDR (0x03009888)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_DEST_OUTER_STRIDE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_DEST_OUTER_STRIDE_REG_ADDR (0x03009890)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_DEST_OUTER_END_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_DEST_OUTER_END_REG_ADDR (0x03009898)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_DEST_OUTER_ADDRESS_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_DEST_OUTER_ADDRESS_REG_ADDR (0x030098A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_DEST_FACE_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_DEST_FACE_SIZE_REG_ADDR (0x030098A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_SRC_GEN_ADDRESS_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_SRC_GEN_ADDRESS_REG_ADDR (0x030098B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_DEST_GEN_ADDRESS_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_DEST_GEN_ADDRESS_REG_ADDR (0x030098B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_MISC_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_R_MISC_REG_ADDR (0x030098C0)

//==============================================================================
// Register File: tt_rocc_cpu7_address_gen_w
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_REG_FILE_BASE_ADDR (0x03009A00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_REG_FILE_SIZE (0x000000C8)

#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_SRC_BANK_CURRENT_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_SRC_BANK_CURRENT_REG_ADDR (0x03009A00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_SRC_BANK_BASE_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_SRC_BANK_BASE_REG_ADDR (0x03009A08)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_SRC_BANK_SIZE_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_SRC_BANK_SIZE_REG_ADDR (0x03009A10)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_SRC_BANK_SKIP_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_SRC_BANK_SKIP_REG_ADDR (0x03009A18)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_SRC_INNER_STRIDE_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_SRC_INNER_STRIDE_REG_ADDR (0x03009A20)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_SRC_INNER_END_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_SRC_INNER_END_REG_ADDR (0x03009A28)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_SRC_INNER_ADDRESS_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_SRC_INNER_ADDRESS_REG_ADDR (0x03009A30)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_SRC_OUTER_STRIDE_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_SRC_OUTER_STRIDE_REG_ADDR (0x03009A38)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_SRC_OUTER_END_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_SRC_OUTER_END_REG_ADDR (0x03009A40)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_SRC_OUTER_ADDRESS_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_SRC_OUTER_ADDRESS_REG_ADDR (0x03009A48)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_SRC_FACE_SIZE_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_SRC_FACE_SIZE_REG_ADDR (0x03009A50)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_DEST_BANK_CURRENT_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_DEST_BANK_CURRENT_REG_ADDR (0x03009A58)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_DEST_BANK_BASE_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_DEST_BANK_BASE_REG_ADDR (0x03009A60)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_DEST_BANK_SIZE_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_DEST_BANK_SIZE_REG_ADDR (0x03009A68)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_DEST_BANK_SKIP_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_DEST_BANK_SKIP_REG_ADDR (0x03009A70)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_DEST_INNER_STRIDE_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_DEST_INNER_STRIDE_REG_ADDR (0x03009A78)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_DEST_INNER_END_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_DEST_INNER_END_REG_ADDR (0x03009A80)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_DEST_INNER_ADDRESS_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_DEST_INNER_ADDRESS_REG_ADDR (0x03009A88)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_DEST_OUTER_STRIDE_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_DEST_OUTER_STRIDE_REG_ADDR (0x03009A90)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_DEST_OUTER_END_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_DEST_OUTER_END_REG_ADDR (0x03009A98)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_DEST_OUTER_ADDRESS_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_DEST_OUTER_ADDRESS_REG_ADDR (0x03009AA0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_DEST_FACE_SIZE_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_DEST_FACE_SIZE_REG_ADDR (0x03009AA8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_SRC_GEN_ADDRESS_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_SRC_GEN_ADDRESS_REG_ADDR (0x03009AB0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_DEST_GEN_ADDRESS_REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_DEST_GEN_ADDRESS_REG_ADDR (0x03009AB8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_MISC_REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_ADDRESS_GEN_W_MISC_REG_ADDR (0x03009AC0)

//==============================================================================
// Register File: tt_rocc_cpu7_simple_cmd_buf
//==============================================================================

#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_REG_FILE_BASE_ADDR (0x03009C00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_REG_FILE_SIZE (0x00000148)

#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_IE_REG_OFFSET (0x00000000)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_IE_REG_ADDR (0x03009C00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_IP_REG_OFFSET (0x00000008)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_IP_REG_ADDR (0x03009C08)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_0_REG_OFFSET (0x00000010)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_0_REG_ADDR (0x03009C10)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_1_REG_OFFSET (0x00000018)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_1_REG_ADDR (0x03009C18)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_SRC_ADDR_REG_OFFSET (0x00000020)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_SRC_ADDR_REG_ADDR (0x03009C20)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_2_REG_OFFSET (0x00000028)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_2_REG_ADDR (0x03009C28)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_3_REG_OFFSET (0x00000030)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_3_REG_ADDR (0x03009C30)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_SRC_COORD_REG_OFFSET (0x00000038)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_SRC_COORD_REG_ADDR (0x03009C38)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_DEST_ADDR_REG_OFFSET (0x00000040)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_DEST_ADDR_REG_ADDR (0x03009C40)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_4_REG_OFFSET (0x00000048)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_4_REG_ADDR (0x03009C48)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_5_REG_OFFSET (0x00000050)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_5_REG_ADDR (0x03009C50)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_DEST_COORD_REG_OFFSET (0x00000058)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_DEST_COORD_REG_ADDR (0x03009C58)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_LEN_BYTES_REG_OFFSET (0x00000060)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_LEN_BYTES_REG_ADDR (0x03009C60)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_REQ_VC_REG_OFFSET (0x00000068)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_REQ_VC_REG_ADDR (0x03009C68)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_6_REG_OFFSET (0x00000070)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_6_REG_ADDR (0x03009C70)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_7_REG_OFFSET (0x00000078)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_7_REG_ADDR (0x03009C78)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESP_VC_REG_OFFSET (0x00000080)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESP_VC_REG_ADDR (0x03009C80)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_8_REG_OFFSET (0x00000088)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_8_REG_ADDR (0x03009C88)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_9_REG_OFFSET (0x00000090)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_9_REG_ADDR (0x03009C90)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_TR_ID_REG_OFFSET (0x00000098)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_TR_ID_REG_ADDR (0x03009C98)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_10_REG_OFFSET (0x000000A0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_10_REG_ADDR (0x03009CA0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_11_REG_OFFSET (0x000000A8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_11_REG_ADDR (0x03009CA8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_MCAST_EXCLUDE_REG_OFFSET (0x000000B0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_MCAST_EXCLUDE_REG_ADDR (0x03009CB0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_12_0__REG_OFFSET (0x000000B8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_12_0__REG_ADDR (0x03009CB8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_12_1__REG_OFFSET (0x000000C0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_12_1__REG_ADDR (0x03009CC0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_12_2__REG_OFFSET (0x000000C8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_12_2__REG_ADDR (0x03009CC8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_12_3__REG_OFFSET (0x000000D0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_12_3__REG_ADDR (0x03009CD0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_12_4__REG_OFFSET (0x000000D8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_12_4__REG_ADDR (0x03009CD8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_12_5__REG_OFFSET (0x000000E0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_12_5__REG_ADDR (0x03009CE0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_12_6__REG_OFFSET (0x000000E8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_12_6__REG_ADDR (0x03009CE8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_12_7__REG_OFFSET (0x000000F0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_12_7__REG_ADDR (0x03009CF0)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_INLINE_DATA_REG_OFFSET (0x000000F8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_INLINE_DATA_REG_ADDR (0x03009CF8)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_13_REG_OFFSET (0x00000100)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_13_REG_ADDR (0x03009D00)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_MCAST_DESTS_REG_OFFSET (0x00000108)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_MCAST_DESTS_REG_ADDR (0x03009D08)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_14_REG_OFFSET (0x00000110)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_14_REG_ADDR (0x03009D10)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_15_REG_OFFSET (0x00000118)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_15_REG_ADDR (0x03009D18)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_16_REG_OFFSET (0x00000120)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_16_REG_ADDR (0x03009D20)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_17_REG_OFFSET (0x00000128)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_RESERVED_17_REG_ADDR (0x03009D28)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_PACKET_TAGS_REG_OFFSET (0x00000130)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_PACKET_TAGS_REG_ADDR (0x03009D30)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_DEBUG_REG_OFFSET (0x00000138)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_DEBUG_REG_ADDR (0x03009D38)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_MISC_REG_OFFSET (0x00000140)
#define TT_ROCC_ACCEL_TT_ROCC_CPU7_SIMPLE_CMD_BUF_MISC_REG_ADDR (0x03009D40)

#endif
